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MC14581

MC14581 DataSheet Motorola, Inc 4-Bit Arithmetic Logic Unit

4-Bit Arithmetic Logic Unit

Motorola,

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---Full Text Search Engine--- MC14581 Motorola,
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MC14581 MC14581BCL MC14581BCP MC14581BDW MC14581B ON0940

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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MC14581B 4-Bit Arithmetic Logic Unit
The MC14581B is a CMOS 4-bit ALU capable of providing 16 functions of two Boolean variables and 16 binary arithmetic operations on two 14-bit words. The level of the mode control input determines whether the output function is logic or arithmetic. The desired logic function is selected by applying the appropriate binary word to the select inputs (S0 thru S3) with the mode control input high, while the desired arithmetic operation is selected by applying a low voltage to the mode control input, the required level to carry in, and the appropriate word to the select inputs. The word inputs and function outputs can be operated with either active high or active low data. Carry propagate (P) and carry generate (G) outputs are provided to allow a full look-ahead carry scheme for fast simultaneous carry generation for the four bits in the package. Fast arithmetic operations on long words are obtainable by using the MC14582B as a second order look ahead block. An inverted ripple carry input (Cn) and a ripple carry output (Cn+4) are included for ripple through operation. When the device is in the subtract mode (LHHL), comparison of two 4-bit words present at the A and B inputs is provided using the A = B output. It assumes a high-level state when indicating equality. Also, when the ALU is in the subtract mode the Cn+4 output can be used to indicate relative magnitude as shown in this table:
Data Level Active High Cn H L H L L H L H Cn+4 H H L L L L H H Magnitude A B A<B A>B A B L SUFFIX CERAMIC CASE 623
P SUFFIX PLASTIC CASE 709
DW SUFFIX SOIC CASE 751E
ORDERING INFORMATION
MC14XXXBCP MC14XXXBCL MC14XXXBDW Plastic Ceramic SOIC
TA = - 55 to 125C for all packages.
PIN ASSIGNMENT
v
B0 A0 S3 S2 S1 S0 Cn MC F0 F1 F2 VSS
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
VDD A1 B1 A2 B2 A3 B3 G Cn+4 P A=B F3
Active Low
w AvB
A<B A>B A B
w
IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII
MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol VDD Parameter DC Supply Voltage Value Unit V V - 0.5 to + 18.0  10 500 - 65 to + 150 260 Vin, Vout Iin, Iout PD Tstg TL Input or Output Voltage (DC or Transient) - 0.5 to VDD + 0.5 Input or Output Current (DC or Transient), per Pin Power Dissipation, per Package Storage Temperature Lead Temperature (8-Second Soldering) mA mW
* * * * *
Functional and Pinout Equivalent to 74181. Diode Protection on All Inputs All Outputs Buffered Supply Voltage Range = 3.0 Vdc to 18 Vdc Capable of Driving Two Low-power TTL Loads or One Low-power Schottky TTL Load over the Rated Temperature Range
_C _C
* Maximum Ratings are those values beyond which damage to the device may occur. Temperature Derating: Plastic "P and D/DW" Packages: - 7.0 mW/_C From 65_C To 125_C Ceramic "L" Packages: - 12 mW/_C From 100_C To 125_C
REV 3 1/94
(c)MOTOROLA CMOS LOGIC DATA Motorola, Inc. 1995
MC14581B 1
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic Symbol VOL VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 VIH 5.0 10 15 IOH Source 5.0 5.0 10 15 IOL 5.0 10 15 -- 5.0 10 15 5.0 10 15 - 1.2 - 0.64 - 1.6 - 4.2 0.64 1.6 4.2 -- -- -- -- -- -- -- -- -- -- -- -- 5.0 10 20 - 1.0 - 0.51 - 1.3 - 3.4 0.51 1.3 3.4 -- -- -- -- - 1.7 - 0.88 - 2.25 - 8.8 0.88 2.25 8.8 5.0 0.005 0.010 0.015 -- -- -- -- -- -- -- 7.5 5.0 10 20 - 0.7 - 0.36 - 0.9 - 2.4 0.36 0.9 2.4 -- -- -- -- -- -- -- -- -- -- -- -- 150 300 600 mAdc 3.5 7.0 11 -- -- -- 3.5 7.0 11 2.75 5.50 8.25 -- -- -- 3.5 7.0 11 -- -- -- mAdc Min -- -- -- - 55_C 25_C 125_C Max Min -- -- -- Typ # 0 0 0 Max Min -- -- -- Max Unit Vdc Output Voltage Vin = VDD or 0 "0" Level 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 Vdc "1" Level Vin = 0 or VDD Input Voltage "0" Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) "1" Level (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Input Capacitance (Vin = 0) Quiescent Current (Per Package) Total Supply Current** (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) VIL -- -- -- -- -- -- 2.25 4.50 6.75 -- -- -- VOH 4.95 9.95 14.95 4.95 9.95 14.95 5.0 10 15 4.95 9.95 14.95 Vdc Vdc Sink Cin IDD pF Adc IT IT = (1.8 A/kHz) f + IDD IT = (3.7 A/kHz) f + IDD IT = (5.5 A/kHz) f + IDD Adc #Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. ** The formulas given are for the typical characteristics only at 25_C. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL - 50) Vfk where: IT is in A (per package), CL in pF, V = (VDD - VSS) in volts, f in kHz is input frequency, and k = 0.008. This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS  (Vin or Vout)  VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
MC14581B 2
MOTOROLA CMOS LOGIC DATA
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)
Characteristic Output Rise and Fall Time tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns Symbol tTLH, tTHL VDD 5.0 10 15 Min -- -- -- Typ # 100 50 40 Max 200 100 80 Unit ns Propagation Delay Time Sum in to Sum Out tPLH, tPHL = (1.7 ns/pF) CL + 620 ns tPLH, tPHL = (0.66 ns/pF) CL + 217 ns tPLH, tPHL = (0.5 ns/pF) CL + 155 ns Sum in to Sum Out (Logic Mode) tPLH, tPHL = (1.7 ns/pF) CL + 520 ns tPLH, tPHL = (0.66 ns/pF) CL + 182 ns tPLH, tPHL = (0.5 ns/pF) CL + 155 ns Sum in to A = B tPLH, tPHL = (1.7 ns/pF) CL + 870 ns tPLH, tPHL = (0.66 ns/pF) CL + 297 ns tPLH, tPHL = (0.5 ns/pF) CL + 220 ns Sum in to P or G tPLH, tPHL = (1.7 ns/pF) CL + 400 ns tPLH, tPHL = (0.66 ns/pF) CL + 147 ns tPLH, tPHL = (0.5 ns/pF) CL + 105 ns Sum in to Cn+4 tPLH, tPHL = (1.7 ns/pF) CL + 530 ns tPLH, tPHL = (0.66 ns/pF) CL + 187 ns tPLH, tPHL = (0.5 ns/pF) CL + 135 ns Carry in to Sum Out tPLH, tPHL = (1.7 ns/pF) CL + 295 ns tPLH, tPHL = (0.66 ns/pF) CL + 112 ns tPLH, tPHL = (0.5 ns/pF) CL + 80 ns Carry in to Cn+4 tPLH, tPHL = (1.7 ns/pF) CL + 220 ns tPLH, tPHL = (0.66 ns/pF) CL + 87 ns tPLH, tPHL = (0.5 ns/pF) CL + 60 ns tPLH, tPHL 5.0 10 15 tPLH, tPHL 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 tPLH, tPHL 5.0 10 15 5.0 10 15 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 705 250 180 605 215 180 955 330 245 485 180 130 615 220 160 380 145 105 305 120 85 1410 500 360 ns 1210 430 360 ns 1910 660 490 ns 970 360 260 ns 1230 440 360 ns 760 290 210 ns 610 240 170 ns tPLH, tPHL tPLH, tPHL tPLH tPLH, tPHL * The formulas given are for the typical characteristics only at 25_C. #Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance.
AC TEST SETUP REFERENCE TABLE
AC Paths Test Sumin to Sumout Delay Time Sumin to P Delay Time Sumin to G Delay Time Sumin to Cn+4 Delay Time Cn to Sumout Delay Time Cn to Cn+4 Delay Time Sumin to A = B Delay Time Sumin to Sumout Delay Time (Logic Mode) Inputs A0 A0 B0 B0 Cn Cn A0 Outputs Any F P G Cn+y Any F Cn+4 A=B DC Data Inputs To VSS Remaining A's Cn Remaining A's Cn All A's Cn All A's Cn All A's All A's All B's Remaining A's All A's To VDD All B's All B's Remaining B's Remaining B's All B's All B's Cn Mode Add Add Add Add Add Add Sub Exclusive OR Fig. 3 Waveform #1 #1 #1 #2 #1 #1 #2
B0
Any F
M
#2
MOTOROLA CMOS LOGIC DATA
MC14581B 3
VDD
Vout = VOH
VDD
Vout = VOH
S0 S1 S2 S3 VDD A0 A1 A2 A3 B0 B1 B2 B3 Cn MC VSS
F0 F1 F2 F3 IOH VDD
S0 S1 S2 S3 A0 A1 A2 A3 B0 B1 B2 B3 Cn MC VSS
F0 F1 F2 F3 A=B Cn+4 G P EXTERNAL POWER SUPPLY IOH
A=B Cn+4 G P EXTERNAL POWER SUPPLY
HIGH FOR ALL OUTPUTS EXCEPT Cn+4
HIGH FOR ALL OUTPUTS EXCEPT Cn+4
Figure 1. Typical Source Current Test Circuit
Figure 2. Typical Sink Current Test Circuit
VDD
LOAD A TP out 50 pF
20 ns 20 ns TPin 90% 10% tTLH tPHL VOH 10% tTHL tTHL 90% #2 TPout tPHL 10% tTLH tPLH VOH VOL VOL VDD 0V
TPin PULSE GENERATOR SEE AC TEST SETUP REFERENCE TABLE FOR CONNECTIONS
S0 S1 S2 S3 F0 A0 F1 A1 A2 F2 A3 F3 B0 B1 A=B B2 Cn+4 B3 G Cn P MC
LOAD A LOAD A LOAD A LOAD A LOAD A LOAD A LOAD A LOAD A
#1 TPout tPLH
Figure 3. Switching Time Test Circuit and Waveforms
VDD LOAD A TPout
S0 S1 S2 S3 TPin PULSE GENERATOR DUTY CYCLE = 50% A0 A1 A2 A3 B0 B1 B2 B3 Cn MC F0 F1 F2 F3 A=B Cn+4 G P LOAD A LOAD A LOAD A LOAD A LOAD A LOAD A LOAD A LOAD A TPin 20 ns
50 pF
90% 50% VARIABLE WIDTH
20 ns VDD 10% 0V
Figure 4. Dynamic Power Dissipation Test Circuit and Waveform
MC14581B 4
MOTOROLA CMOS LOGIC DATA
BLOCK DIAGRAM (ACTIVE LOW)
FUNCTION SELECT INPUTS 3 4 5 6 S0 S1 S2 S3 A0 F0 A1 F1 A2 F2 A3 F3 B0 B1 A=B B2 Cn+4 B3 G Cn P MC 3 4 5 6
BLOCK DIAGRAM (ACTIVE HIGH)
VDD = PIN 24 VSS = PIN 12 9 10 11 13
WORD A
2 23 21 19 1 22 20 18
OUTPUT FUNCTION
2 23 21 19 1 22 20 18 7 8
WORD B
14 COMPARISON OUTPUT 16 RIPPLE CARRY OUTPUT 17 LOOK AHEAD 15 CARRY OUTPUTS
CARRY IN 7 MODE CONTROL 8
S0 S1 S2 S3 A0 F0 A1 F1 A2 F2 A3 F3 B0 B1 A=B B2 Cn+4 B3 G Cn P MC
9 10 11 13 14 16 17 15
TRUTH TABLE
Function Select Inputs/Outputs Active Low Logic Function (MC = H) A AB A+B Logic "1" A+B B A AB A B A+B Logic "0" AB AB A B B A+B Arithmetic* Function (MC = L, Cn = L) A minus 1 AB minus 1 AB minus 1 minus 1 A plus (A + B) AB plus (A + B) A minus B minus 1 A+B A plus (A + B) A plus B AB plus (A + B) A+B A plus A AB plus A AB plus A A Inputs/Outputs Active High Logic Function (MC = H) A A+B AB Logic "0" AB B A AB A+B A B AB Logic "1" A+B A+B A B B Arithmetic* Function (MC = L, Cn = H) A A+B A+B minus 1 A plus AB (A + B) plus AB A minus B minus 1 AB minus 1 A plus AB A plus B (A + B) plus AB AB minus 1 A plus A (A + B) plus A (A + B) plus A A minus 1
S3 L L L L L L L L H H H H H H H H
S2 L L L L H H H H L L L L H H H H
S1 L L H H L L H H L L H H L L H H
S0 L H L H L H L H L H L H L H L H
* Expressed as two's complements. For arithmetic function with C n in the opposite state, the resulting function is as shown plus 1.
MOTOROLA CMOS LOGIC DATA
MC14581B 5
OUTLINE DIMENSIONS
L SUFFIX CERAMIC DIP PACKAGE CASE 623-05 ISSUE M
24 13 NOTES: 1. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 2. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE POSITION AT SEATING PLANE AT MAXIMUM MATERIAL CONDITION (WHEN FORMED PARALLEL). DIM A B C D F G J K L M N MILLIMETERS MIN MAX 31.24 32.77 12.70 15.49 4.06 5.59 0.41 0.51 1.27 1.52 2.54 BSC 0.20 0.30 3.18 4.06 15.24 BSC 0_ 15 _ 0.51 1.27 INCHES MIN MAX 1.230 1.290 0.500 0.610 0.160 0.220 0.016 0.020 0.050 0.060 0.100 BSC 0.008 0.012 0.125 0.160 0.600 BSC 0_ 15_ 0.020 0.050
B
1 12
A
SEATING PLANE
F
C
L G D N K M J
P SUFFIX PLASTIC DIP PACKAGE CASE 709-02 ISSUE C
24 13 NOTES: 1. POSITIONAL TOLERANCE OF LEADS (D), SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM MATERIAL CONDITION, IN RELATION TO SEATING PLANE AND EACH OTHER. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. DIM A B C D F G H J K L M N MILLIMETERS MIN MAX 31.37 32.13 13.72 14.22 3.94 5.08 0.36 0.56 1.02 1.52 2.54 BSC 1.65 2.03 0.20 0.38 2.92 3.43 15.24 BSC 0_ 15_ 0.51 1.02 INCHES MIN MAX 1.235 1.265 0.540 0.560 0.155 0.200 0.014 0.022 0.040 0.060 0.100 BSC 0.065 0.080 0.008 0.015 0.115 0.135 0.600 BSC 0_ 15_ 0.020 0.040
B
1 12
A N K H G F D
SEATING PLANE
C
L
M
J
MC14581B 6
MOTOROLA CMOS LOGIC DATA
OUTLINE DIMENSIONS
DW SUFFIX PLASTIC SOIC PACKAGE CASE 751E-04 ISSUE E
-A-
24 13 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 15.25 15.54 7.40 7.60 2.35 2.65 0.35 0.49 0.41 0.90 1.27 BSC 0.23 0.32 0.13 0.29 0_ 8_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.601 0.612 0.292 0.299 0.093 0.104 0.014 0.019 0.016 0.035 0.050 BSC 0.009 0.013 0.005 0.011 0_ 8_ 0.395 0.415 0.010 0.029
-B-
12X
P 0.010 (0.25)
M
B
M
1
12
24X
D 0.010 (0.25)
M
J TA
S
B
S
F R C -T-
SEATING PLANE X 45 _
M
22X
G
K
DIM A B C D F G J K M P R
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MOTOROLA CMOS LOGIC DATA 
*MC14581B/D*
MC14581B MC14581B/D 7