FUJITSU SEMICONDUCTOR DATA SHEET DS07-16502-3E 32-Bit Proprietary Microcontroller CMOS FR60 MB91301 Series MB91302A/V301A DESCRIPTION The MB91301 series are a line of microcontrollers based on a 32-bit RISC CPU core (FR family) , incorporating a variety of I/O resources and a bus control mechanism for embedded control that requires the processing of a high-performance, fast CPU as well as an SDRAM interface that can connect SDRAM directly to the chip. The large address space supported by the 32-bit CPU addressing means that operation is primarily based on external bus access although instruction cache memory of 4 Kbytes and RAM of 4 Kbytes( for data) are included for high-speed execution of CPU instructions. The MB91302A and MB91V301A are FR60 products based on the FR30/40 CPU with enhanced bus access for higher speed operation. The device specifications include a D/A converter to facilitate motor control and are ideal for use in DVD players that support fly-by transfer. FEATURES The MB91301 series is a line of ICs with various programs embedded in internal ROM. ROM variation Product name Built-in the real Built-in IPL time OS version (Internal Program Loader) version User ROM version Without ROM version MB91302A (Continued) PACKAGES 144-pin, Plastic LQFP 179-pin, Ceramic PGA (FPT-144P-M12) (PGA-179C-A03) MB91301 Series 1. FR CPU * 32-bit RISC, load/store architecture, 5-stage pipeline * 68 MHz internal operating frequency (Max) [external (Max) 68 MHz] (when using PLL with base frequency (Max) = 17 MHz) * General purpose registers : 32 bitsx16 * 16-bit fixed length instructions (basic instructions) , 1 instruction per cycle * Instruction set optimized for embedded applications: Memory-to-memory transfer, bit manipulation, barrel shift etc. * Instructions adapted for high-level languages : Function entry/exit instructions, multiple-register load/store instructions * Easier assembler coding : Register interlock function * Branch instructions with delay slots : Reduced overhead time in branch executions * Built-in multiplier with instruction-level support Signed 32-bit multiplication : 5 cycles Signed 16-bit multiplication : 3 cycles * Interrupt (PC, PS save) : 6 cycles, 16 priority levels 2. Bus interface * * * * * * * Operating frequency : Max 68 MHz (when using SDRAM) Full 24-bit address output (16 Mbytes memory space) 8-bit, 16-bit or 32-bit data input/output Built-in pre-fetch buffer Unused data and address pins can be used as general-purpose input/output ports. Eight fully independent chip select outputs, can be set in minimum 64 Kbytes units. Supports the following memory interfaces Asynchronous SRAM, asynchronous ROM/Flash Page mode ROM/Flash ROM (selectable page size = 1, 2, 4, or 8) Burst mode ROM/Flash ROM (MBM29BL160D/161D/162D) SDRAM (FCRAM Type, CAS Latency 1 to 8, 2/4 bank products.) Address/Data multiplex bus (only 8/16-bit width) Basic bus cycle : 2 cycles Automatic wait cycle generation function can insert wait cycles, independently programmable for each memory area. RDY input for external wait cycles Endian setting of byte ordering (Big/Little) CS0 area only for big endian Prohibition setting of write (only for Read) Permission/prohibition setting of fetch into built-in cache Permission/prohibition setting of prefetch function DMA supports fly-by transfer with independent I/O wait control External bus arbitration can be used using BRQ and BGRNT. * * * * * * * * * * * 3. Built-in memory * 4 Kbytes DATA RAM * 4 Kbytes RAM (MB91302A) (Continued) 2 MB91301 Series 4. Instruction cache * * * * * * * * * * * * Size : 4 Kbytes 2-way set associative 128 blocks/way, 4 entries/block Lock function enables program code to be made cache-resident Areas not used for instruction cache can be used as instruction RAM 5-channel (2-channel external-to-external) 3 transfer triggers : External pin, internal peripheral, software Capable of selecting an internal peripheral as a transfer source freely for each channel Addressing using 32-bit full addressing mode (increment, decrement, fixed) Transfer modes : Demand transfer, burst transfer, step transfer, or block transfer Supports fly-by transfer (between external I/O and memory) Selectable transfer data size : 8, 16, or 32-bit 5. DMAC (DMA Controller) 6. Bit search module * Searches words from MSB for position of first 1/0 bit value change 7. Reload Timers * 16-bit timer : 3 channels * Internal clock : 2 clock cycle resolution, divide by 2/8/32 selective 8. UART Full duplex, double buffer UART Independent 3 channels Data length : 7 bits to 9 bits (without parity) , 6 bits to 8 bits (with parity) Asynchronous (start-stop synchronized) or CLK-synchronous communications selectable Multi-processor mode * Built-in 16-bit timer (U-TIMER) as a baud rate generator to generate arbitrary baud rates * External clock can be used as transfer clock * Variety of error detection functions (parity, frame, overrun) * * * * 9. Interrupt controller * External interrupt input : 1 non-maskable interrupt pin and 8 normal interrupt pins (INT0 to INT7) * Internal internal resources : UART, DMAC, A/D, U-TIMER, Delay interrupt, I2C, Free-run timer, Input capture * Programmable priorities (16 levels) for all interrupts except the non-maskable interrupt 10. A/D converter * * * * * 10-bit resolution, 4 channels Successive approximation type, conversion time : 4.1 s at 34 MHz Built-in sample and hold circuit Conversion modes : Single conversion mode, scan conversion mode and repeat conversion mode selectable Conversion triggers : Software, external trigger and built-in timer selectable 11. I2C* interface * Internal 2-channels master/slave transmit/receive * Internal arbitration function, clock synch function 12. Free-run timer * 16 bit : 1channel (Continued) 3 MB91301 Series (Continued) 13. Input capture * 4 channels 14. Other interval timers * 16-bit timer : 3 channels (U-TIMER) * PPG timer : 4 channels * Watchdog timer : 1 channel 15. Other features * Reset resources : watchdog timer/software reset/external reset (INIT pin) * Power-saving modes : Stop mode, sleep mode * Clock control Gear function : Allows arbitrary different operating clock frequencies to be set for the CPU and peripherals. You can select one of the 16 gear clock factors of 1/1 to 1/16. PLL multiplication can also be selected. Note, however, that peripherals operate at a maximum of 34 MHz. * CMOS technology : 0.25 m * Power supply (analog power supply): 3.3 V 0.3 V (internal regulator used) * : Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these components in an I2C system provided that the system conforms to the I2C Standard Specification as defined by Philips. PRODUCT LINEUP MB91302A Type Mask ROM product (for volume production) 4 Kbytes (only for data) 4 Kbytes ROM has non-ROM model, the optimal real time OS internal model*1, and the IPL (Internal Program Loader) internal model*2 by adding the user ROM model. LQFP-144 (0.4 mm pitch) MB91V301A Evaluation version (For evaluation and development) 16 Kbytes (data 8 KB+8 KB) RAM ROM 8 Kbytes (RAM) DSU Package DSU4 PGA-179 *1 : The Fujitsu product of real time OS REALOS/FR by conforming to the ITRON 3.0 is stored and optimized with the MB91302A. *2 : The ROM stores the IPL (Internal Program Loader) . Loading various programs can be executed from the external system by the internal UART/SIO. Using this function, for example, writing on board to the Flash memory connected to the external can be executed. 4 MB91301 Series PIN ASSIGNMENTS * MB91302A (TOP VIEW) P91/MCLKE P92/MCLK P93 P94/SRAS/LBA/AS P95/SCAS/BAA P96/SWE/WR VSS VCC A00 A01 A02 A03 A04 A05 A06 A07 VSS VCC A08 A09 A10 A11 A12 A13 A14 A15 VSS P60/A16 P61/A17 P62/A18 P63/A19 P64/A20/SDA0 P65/A21/SCL0 P66/A22/SDA1 P67/A23/SCL1 VCC 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 P13/D11 P14/D12 P15/D13 P16/D14 P17/D15 VSS VCC P20/D16 P21/D17 P22/D18 P23/D19 P24/D20 P25/D21 P26/D22 P27/D23 VSS VCC D24 D25 D26 D27 D28 D29 D30 D31 VSS VCC P80/RDY P81/BGRNT P82/BRQ RD DQMUU/WR0(UUB) P85/DQMUL/WR1(ULB) P86/DQMLU/WR2(LUB) P87/DQMLL/WR3(LLB) P90/SYSCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 D10/P12 D09/P11 D08/P10 VCC VSS D07/P07 D06/P06 D05/P05 D04/P04 D03/P03 D02/P02 D01/P01 D00/P00 VCC VSS CS7/PA7 CS6/PA6 CS5/PPG2/PA5 CS4/TRG2/PA4 CS3/PA3 CS2/PA2 CS1/PA1 CS0/PA0 VCC NMI INIT MD2 MD1 MD0 VCC VSS X1 X0 VCC IORD/PB7 IOWR/PB6 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 DEOP1/PPG1/PB5 DACK1/TRG1/PB4 DREQ1/PB3 DEOP0/PB2 DACK0/PB1 DREQ0/PB0 C VSS TIN2/TRG3/PH2 TIN1/PPG3/PH1 TIN0/PH0 TRG0/PJ7 PPG0/PJ6 SCK1/PJ5 SOT1/PJ4 SIN1/PJ3 SCK0/PJ2 SOT0/PJ1 SIN0/PJ0 VCC INT7/SCK2/PG7 INT6/SOT2/PG6 INT5/SIN2/PG5 INT4/ATG/PG4/FRCK INT3/PG3/ICU3 INT2/PG2/ICU2 INT1/PG1/ICU1 INT0/PG0/ICU0 AVSS/AVRL AN0 AN1 AN2 AN3 AVR AVRH AVCC (FPT-144P-M12) 5 MB91301 Series * MB91V301A (TOP VIEW) INDEX 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 5 7 10 15 16 20 21 25 26 30 33 37 39 43 50 178 179 4 9 13 14 19 22 27 31 34 38 42 44 52 174 177 2 3 8 12 18 24 28 32 36 41 47 49 55 172 173 176 180 6 11 17 23 29 35 40 45 48 54 60 46 51 53 58 61 56 57 59 65 62 63 64 66 68 69 67 70 74 73 72 71 80 77 76 75 91 85 81 79 78 168 169 171 175 1 165 166 167 170 161 162 163 164 160 157 159 158 156 154 153 152 155 149 147 146 151 148 143 141 136 150 144 138 135 130 125 119 113 107 101 96 90 86 83 82 145 139 137 131 126 122 118 114 108 102 98 93 92 87 84 142 134 132 128 124 121 117 112 109 104 103 99 94 89 88 140 133 129 127 123 120 116 115 111 110 106 105 100 97 95 A B C D E F G H J K L M N P R (PGA-179C-A03) 6 MB91301 Series * MB91V301A Pin No. Table No. PIN Pin Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 E5 C3 C4 B3 A1 D5 A2 C5 B4 A3 D6 C6 B5 B6 A4 A5 D7 C7 B7 A6 A7 B8 D8 C8 A8 A9 B9 C9 D9 A10 N.C. P13/D11 VSS VCC P14/D12 P15/D13 P16/D14 P17/D15 VSS VCC P20/D16 P21/D17 P22/D18 P23/D19 P24/D20 P25/D21 P26/D22 P27/D23 VSS VCC D24 D25 D26 D27 VSS VCC D28 D29 D30 D31 No. 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 PIN B10 C10 A11 B11 D10 C11 A12 B12 A13 D11 C12 B13 A14 B14 D12 E11 C13 D13 C14 A15 E12 B15 E13 D14 C15 F12 F13 E14 F14 D15 Pin Name VSS VCC P80/RDY P81/BGRNT P82/BRQ RD DQMUU/WR0 (UUB) P85/DQMUL/WR1 (ULB) P86/DQMLU/WR2 (LUB) P87/DQMLL/WR3 (LLB) VSS VCC P90/SYSCLK P91/MCLKE P92/MCLK P93 VSS VCC P94/SRAS/LBA/AS P95/SCAS/BAA P96/SWE/WR VSS VCC A00 A01 A02 A03 A04 A05 A06 No. 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 PIN E15 G12 G13 G14 F15 G15 H14 H12 H13 H15 J15 J14 J13 J12 K15 K14 K13 L15 L14 K12 L13 M15 M14 N15 L12 M13 N14 P15 P14 M12 Pin Name A07 VSS VCC A08 A09 A10 A11 A12 A13 A14 A15 VSS VCC P60/A16 P61/A17 P62/A18 P63/A19 SDA0/P64/A20 SCL0/P65/A21 SDA1/P66/A22 SCL1/P67/A23 VCC VCC EWR3 EWR2 EWR1 EWR0 ECS EMRAM ICD3 (Continued) 7 MB91301 Series (Continued) No. PIN 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 L11 N13 N12 P13 R15 M11 R14 N11 P12 R13 M10 N10 P11 P10 R12 R11 M9 N9 P9 R10 R9 P8 M8 N8 R8 R7 P7 N7 M7 R6 Pin Name ICD2 ICD1 ICD0 VSS VCC BREAK ICLK ICS2 ICS1 ICS0 TRST C AVCC AVRH AVR AN3 AN2 AN1 AN0 AVSS/AVRL INT0/PG0/ICU0 INT1/PG1/ICU1 INT2/PG2/ICU2 INT3/PG3/ICU3 INT4/ATG/PG4/FRCK INT5/SIN2/PG5 INT6/SOT2/PG6 INT7/SCK2/PG7 VCC SIN0/PJ0 No. 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 PIN P6 N6 R5 P5 M6 N5 R4 P4 R3 M5 N4 P3 R2 P2 M4 L5 N3 M3 N2 R1 L4 P1 L3 M2 N1 K4 K3 L2 K2 M1 Pin Name SOT0/PJ1 SCK0/PJ2 SIN1/PJ3 SOT1/PJ4 SCK1/PJ5 PPG0/PJ6 TRG0/PJ7 TIN0/PH0 TIN1/PPG3/PH1 TIN2/TRG3/PH2 VSS C DREQ0/PB0 DACK0/PB1 DEOP0/PB2 DREQ1/PB3 No. 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 PIN L1 J4 J3 J2 K1 J1 H2 H4 H3 H1 G1 G2 G3 G4 F1 F2 F3 E1 E2 F4 E3 D1 D2 C1 E4 D3 C2 B1 B2 D4 Pin Name VCC INIT NMI VSS VCC CS0/PA0 CS1/PA1 CS2/PA2 CS3/PA3 CS4/TRG2/PA4 CS5/PPG2/PA5 CS6/PA6 CS7/PA7 VSS VCC D00/P00 D01/P01 D02/P02 D03/P03 VSS VCC D04/P04 D05/P05 D06/P06 D07/P07 VSS VCC D08/P10 D09/P11 D10/P12 DACK1/TRG1/PB4 167 DEOP1/PPG1/PB5 168 IOWR/PB6 IORD/PB7 VCC VSS X0 X1 VSS VCC MD0 MD1 MD2 VCC 169 170 171 172 173 174 175 176 177 178 179 180 8 MB91301 Series PIN DESCRIPTIONS * Except for Power supply, GND, and Tool pins Pin no. MB91302A MB91V301A 166 to 169, 172 to 175 Pin name D00 to D07 I/O circuit type Function External data bus bits 0 to 7. It is available in the external bus mode. Can be used as ports in 8-bit or 16-bit external bus mode. External data bus bits 8 to 15. It is available in the external bus mode. Can be used as ports in 8-bit or 16-bit external bus mode. External data bus bits 16 to 23. It is available in the external bus mode. Can be used as ports in 8-bit external bus mode. External data bus bits 24 to 31. It is available in the external bus mode. External ready input. The pin has this function when external ready input is enabled. General purpose input/output port. The pin has this function when external ready input is disabled. Acknowledge output for external bus release. Outputs "L" when the external bus is released. The pin has this function when output is enabled. General purpose input/output port. The pin has this function when output is disabled for external bus release acknowledge. External bus release request input. Input "1" to request release of the external bus. The pin has this function when input is enabled. General purpose input/output port. The pin has this function when the external bus release request input is disabled. External bus read strobe output. External bus write strobe output. When WR is used as the write strobe, this becomes the byte-enable pin (UUB). Select signal (DQMUU) of D31 to D24 at using of SDRAM. (Continued) 132 to 139 J P00 to P07 D08 to D15 J P10 to P17 D16 to D23 P20 to P27 142 to 144, 1 to 5 178 to 180, 2, 5 to 8 8 to 15 11 to 18 21 to 24, 27 to 30 J 18 to 25 D24 to D31 RDY C 28 33 P80 J BGRNT 29 34 P81 J BRQ 30 35 P82 31 36 RD C J 32 37 WR0/ (UUB) / DQMUU C 9 MB91301 Series Pin no. MB91302A MB91V301A Pin name I/O circuit type Function External bus write strobe output. The pin has this function when WR1 output is enabled. When WR is used as the write strobe, this becomes the byteenable pin (ULB). Select signal (DQMUL) of D23 to D16 at using of SDRAM. General purpose input/output port. The pin has this function when the external bus write-enable output is disabled. External bus write strobe output. The pin has this function when WR2 output is enabled. When WR is used as the write strobe, this becomes the byteenable pin (LUB). Select signal (DQMLU) of D08 to D05 at using of SDRAM. General purpose input/output port. The pin has this function when the external bus write-enable output is disabled. External bus write strobe output. The pin has this function when WR3 output is enabled. When WR is used as the write strobe, this becomes the byteenable pin (LLB). Select signal (DQMLL) of D07 to D00 at using of SDRAM. General purpose input/output port. The pin has this functions when the external bus write-enable output is disabled. System clock output. The pin has this function when system clock output is enabled. This outputs the same clock as the external bus operating frequency. (Output halts in stop mode.) General purpose input/output port. The pin has this function when system clock output is disabled. Clock enable signal for memory. WR1/ (ULB) / DQMUL 33 38 P85 J WR2/ (LUB) / DQMLU 34 39 P86 J WR3/ (LLB) / DQMLL 35 40 P87 J SYSCLK 36 43 P90 MCLKE 37 40 P91 J C General purpose input/output port. The pin has this function when clock enable output is disabled. Memory clock output. The pin has this function when memory clock output is enabled. This outputs the same clock as the external bus operating frequency. (Output halts in sleep mode.) General purpose input/output port. The pin has this function when memory clock output is disabled. MCLK 38 45 P92 39 46 P93 C C General purpose input/output port. (Continued) 10 MB91301 Series Pin no. MB91302A MB91V301A Pin name I/O circuit type Function Address strobe output. The pin has this function when ASE bit of port function register 9 is enabled "1". Address strobe output for burst flash ROM. The pin has this function when ASE bit of port function register 9 is enabled "1". RAS single for SDRAM. This pin has this function when ASE bit of port function register 9 is enabled "1". General purpose input/output port. The pin has this function when ASE bit of port function register 9 is "0" general purpose port. Address advance output for burst Flash ROM. The pin has this function when BAAE bit of port function register (PFR9) is enabled. AS LBA 40 49 SRAS J P94 BAA 41 50 SCAS J CAS signal for SDRAM. This pin has this function when BAAE bit of port function register (PFR9) is enabled. General purpose input/output port. The pin has this function when BAAE bit of port function register is general purpose port. Memory write strobe output. This pin has this function when WRXE bit of port function register is enabled. P95 WR 42 51 SWE J Write output for SDRAM. This pin has this function when WRXE bit of port function register is enabled. General purpose input/output port. This pin has this function when WRXE bit of port function register is general purpose port. P96 45 to 52 55 to 62 54 to 61 64 to 71 A00 to A07 A08 to A15 A16 to A19 64 to 67 74 to 77 P60 to P63 J C C External address bits 0 to 7. External address bits 8 to 15. External address bits 16 to 19. It is available in external bus mode. Can be used as ports when external address bus is not used. (Continued) 11 MB91301 Series Pin no. MB91302A MB91V301A Pin name I/O circuit type Function Data input pin for I2C bus function. This function is enable when typical operation of I2C is enable. The port output must remains off unless intentionally turned on. (Open drain output) (This function is only for MB91302A, MB91V301A.) SDA0 68 78 A20 T External address bus bit 20. This function is enable during prohibited I2C operation and using external bus. General-purpose I/O port. This function is enable during prohibited I2C and nonused external address bus. CLK input pin for I2C bus function. This function is enable when typical operation of I2C is enable. The port output must remains off unless intentionally turned on. (open drain output) (This function is only for MB91302A, MB91V301A.) P64 SCL0 69 79 A21 T External address bus bit 21. This function is enable during prohibited I2C operation and using external bus. General-purpose I/O port. This function is enable during prohibited I2C and nonused external address bus. DATA input pin for I2C bus function. This function is enable when typical operation of I2C is enable. The output must remains off unless intentionally turned on. (open drain output) (This function is only for MB91302A, MB91V301A.) P65 SDA1 70 80 A22 T External address bus bit 20. This function is enable during prohibited I2C operation and using external bus. General-purpose I/O port. This function is enable during prohibited I2C and nonused external address bus. (Continued) P66 12 MB91301 Series Pin no. MB91302A MB91V301A Pin name I/O circuit type Function CLK input pin for I2C bus function. This function is enable when typical operation of I2C is enable. The port output must remains off unless intentionally turned on. (open drain output) (This function is only for MB91302A, MB91V301A.) External address bus bit 21. This function is enable during prohibited I2C operation and using external bus. General-purpose I/O port. This function is enable during prohibited I2C operation and nonused external address bus. Analog input pin. External interrupt inputs. These inputs are used continuously when the corresponding external interrupt is enabled. In this case, do not output to these ports unless doing so intentionally. General purpose input/output ports. Input capture input pins. These inputs are used continuously when selected as input capture inputs. In this case, do not output to these ports unless doing so intentionally. External interrupt input. These inputs are used continuously when the corresponding external interrupt is enabled. In this case, do not output to these ports unless doing so intentionally. External trigger input for A/D converter. This input is used continuously when selected as the A/D converter start trigger. In this case, do not output to this port unless doing so intentionally. General purpose input/output ports. External clock input pin for free-run timer. This input is used continuously when selected as the external clock input pin for the free-run timer. In this case, do not output to this port unless doing so intentionally. External interrupt input. These inputs are used continuously when the corresponding external interrupt is enabled. In this case, do not output to these ports unless doing so intentionally. UART2 data input pin. This input is used continuously when UART2 is performing input. In this case, do not output to this port unless doing so intentionally. General purpose input/output port. (Continued) SCL1 71 81 A23 T P67 76 to 79 106 to 109 AN3 to AN0 INT0 to INT3 81 to 84 111 to 114 PG0 to PG3 ICU0 to ICU3 V D INT4 85 115 ATG PG4 FRCK V INT5 86 116 SIN2 PG5 V 13 MB91301 Series Pin no. MB91302A MB91V301A Pin name I/O circuit type Function External interrupt input. This input is used continuously when the corresponding external interrupt is enabled. In this case, do not output to these ports unless doing so intentionally. UART2 data output pin. The pin has this function when UART2 data output is enabled. General purpose input/output port. External interrupt input. This input is used continuously when the corresponding external interrupt is enabled. In this case, do not output to these ports unless doing so intentionally. UART2 clock input/output pin. The pin has this function when UART2 clock output is enabled. General purpose input/output port. UART0 data input pin. This input is used continuously when UART0 is performing input. In this case, do not output to this port unless doing so intentionally. General purpose input/output port. UART0 data output pin. The pin has this function when UART0 data output is enabled. General purpose input/output port. UART0 clock input/output pin. The pin has this function when UART0 clock output is enabled. General purpose input/output port. UART1 data input pin. This input is used continuously when UART1 is performing input. In this case, do not output to this port unless doing so intentionally. General purpose input/output port. UART1 data output pin. The pin has this function when UART1 data output is enabled. General purpose input/output port. UART1 clock input/output pin. The pin has this function when UART1 clock output is enabled. General purpose input/output port. PPG timer output. This pin has this function when PPG0 output is enabled. General purpose input/output port. (Continued) INT6 87 117 SOT2 PG6 V INT7 88 118 SCK2 PG7 SIN0 PJ0 91 121 SOT0 PJ1 92 122 SCK0 PJ2 SIN1 PJ3 94 124 SOT1 PJ4 95 125 SCK1 PJ5 96 126 PPG0 PJ6 U U U U U V 90 120 U 93 123 U 14 MB91301 Series Pin no. MB91302A MB91V301A Pin name I/O circuit type Function External trigger input for PPG timer. This input is used continuously when the corresponding timer input is enabled. In this case, do not output to this port unless doing so intentionally. General purpose input/output port. Reload timer input. This input is used continuously when the corresponding timer input is enabled. In this case, do not output to this port unless doing so intentionally. General purpose input/output port. Reload timer input. This input is used continuously when the corresponding timer input is enabled. In this case, do not output to this port unless doing so intentionally. PPG timer output. The pin has this function when PPG3 output is enabled. General purpose input/output port. Reload timer input. This input is used continuously when the corresponding timer input is enabled. In this case, do not output to this port unless doing so intentionally. 97 127 TRG0 PJ7 TIN0 PH0 TIN1 U 98 128 J 99 129 PPG3 PH1 TIN2 J 100 130 TRG3 PH2 DREQ0 PB0 DACK0 PB1 DEOP0 PB2 J External trigger input for PPG timer. This input is used continuously when the corresponding timer input is enabled. In this case, do not output to this port unless doing so intentionally. General purpose input/output port. External input for DMA transfer requests. This input is used continuously when selected as a DMA activation trigger. In this case, do not output to this port unless doing so intentionally. General purpose input/output port. External acknowledge output for DMA transfer requests. The pin has this function when outputting DMA transfer request acknowledgement is enabled. General purpose input/output port. Completion output for DMA external transfer. The pin has this function when outputting DMA transfer completion is enabled. General purpose input/output port. (Continued) 103 133 J 104 134 J 105 135 J 15 MB91301 Series Pin no. MB91302A MB91V301A Pin name I/O circuit type Function DMA External input for DMA transfer requests. This input is used continuously when selected as a DMA activation trigger. In this case, do not output to this port unless doing so intentionally. General purpose input/output port. The pin has this function when completion output and stop input are disabled for DMA transfer. External acknowledge output for DMA transfer requests. The pin has this function when outputting DMA transfer request acknowledgement is enabled. DREQ1 106 136 PB3 J DACK1 107 137 TRG1 PB4 DEOP1 108 138 PPG1 PB5 IOWR 109 139 PB6 J J J External trigger input for PPG timer. This input is used continuously when the corresponding timer input is enabled. In this case, do not output to this port unless doing so intentionally. General purpose input/output port. Completion output for DMA external transfer. The pin has this function when outputting DMA transfer completion is enabled. PPG timer output. The pin has this function when PPG1 bit is enabled. General purpose input/output port. Write strobe output for DMA fly-by transfer. The pin has this function when outputting a write strobe for DMA fly-by transfer is enabled. General purpose input/output port. The pin has this function when outputting a write strobe for DMA fly-by transfer is disabled. Read strobe output for DMA fly-by transfer. The pin has this function when outputting a read strobe for DMA fly-by transfer is disabled. General purpose input/output port. The pin has this function when outputting a write strobe for DMA fly-by transfer is disabled. Clock (oscillation) input. Clock (oscillation) output. Mode pins 0 to 2. The levels applied to these pins set the basic operating mode. Connect VCC or VSS. External reset input (Reset to initialize settings) ("L" active) NMI (Non Maskable Interrupt) input ("L" active) (Continued) IORD 110 140 PB7 112 113 116 to 118 119 120 143 144 147 to 149 152 053 X0 X1 MD0 to MD2 INIT NMI A A G B M J 16 MB91301 Series (Continued) Pin no. MB91302A MB91V301A Pin name CS0 I/O circuit type Function Chip select 0 output. The pin has this function when chip select 0 output is enabled. General purpose input/output port. The pin has this function when chip select 0 output is disabled. Chip select 1 output. The pin has this function when chip select 1 output is enabled. General purpose input/output port. The pin has this function when chip select 1 output is disabled. Chip select 2 output. The pin has this function when chip select 2 output are enabled. General purpose input/output port. The pin has this function when chip select 2 output is disabled. Chip select 3 output. The pin has this function when chip select 3 output are enabled. General purpose input/output port. The pin has this function when chip select 3 output is disabled. Chip select 4 output. The pin has this function when chip select 4 output is enabled. 122 156 PA0 CS1 J 123 157 PA1 CS2 J 124 158 PA2 CS3 J 125 159 PA3 CS4 J 126 160 TRG2 J External trigger input for PPG timer. This input is used continuously when the corresponding timer input is enabled. In this case, do not output to this port unless doing so intentionally. General purpose input/output port. The pin has this function when chip select 4 output is disabled. Chip select 5 output. The pin has this function when chip select 5 output are enabled. PA4 CS5 127 161 PPG2 PA5 CS6 128 162 PA6 CS7 129 163 PA7 J J J PPG timer output. The pin has this function when PPG2 bit is enabled. General purpose input/output port. The pin has this function when chip select 5 output and PPG timer output are disabled. Chip select 6 output. The pin has this function when chip select 6 output is enabled. General purpose input/output port. The pin has this function when chip select 6 output are disabled. Chip select 7 output. The pin has this function when chip select 7 output are enabled. General purpose input/output port. The pin has this function when chip select 7 output is disabled. 17 MB91301 Series I/O CIRCUIT TYPE Type X1 Circuit Remarks * Oscillation feedback resistance approx. 1 M Clock input A X0 Standby control * CMOS hysteresis input with pull-up resistor P-ch P-ch B N-ch Digital input * CMOS level I/O with standby control * IOL = 4 mA Digital output Digital output P-ch N-ch C Digital input Standby control *Analog input With switch P-ch N-ch D Analog input Control (Continued) 18 MB91301 Series Type Circuit P-ch Remarks *CMOS level output No standby control G N-ch Digital input Pull-up control P-ch P-ch Digital output Digital output N-ch * With Pull-up control * CMOS level I/O with standby control * With Pull-up control * IOL = 4 mA J Digital input Standby control Pull-up control P-ch P-ch Digital output N-ch * With Pull-up control * CMOS level output CMOS level hysteresis input with standby control * IOL = 4 mA K Digital output Digital input Standby control Pull-up control P-ch P-ch Digital output L N-ch Digital output * With Pull-up control * CMOS level output CMOS level hysteresis input no standby control * IOL = 4 mA Digital input * CMOS level hysteresis input no standby control P-ch M N-ch Digital input (Continued) 19 MB91301 Series Type Circuit P-ch Remarks * Output buffer * CMOS level output * IOL = 4 mA Digital output Digital output N N-ch O Digital input * Input buffer * CMOS level input * Input buffer with pull-down * Pull-down resistor value = 25 k approx. (Typ) P N-ch Digital input * Input buffer with Pull-up P-ch Q Digital input P-ch Digital output R N-ch N-ch * I/O buffer with pull-down * CMOS level output * IOL = 4 mA Digital output Digital input * I/O buffer * CMOS level output * IOL = 4 mA P-ch Digital output Digital output S N-ch Digital input (Continued) 20 MB91301 Series (Continued) Type Circuit Pull-up control Digital output with open-drain control Digital output Remarks * N-ch open-drain output * CMOS level I/O with standby control * Without pull-up control * IOL = 4 mA P-ch P-ch N-ch T Digital input P-ch Digital output N-ch U Digital output Digital input * CMOS level output * CMOS level hysteresis input with standby control * 5 V tolerant * IOL = 4 mA P-ch Digital output V N-ch * CMOS level output * CMOS level hysteresis input with standby control * 5 V tolerant * IOL = 4 mA Digital output Digital input 21 MB91301 Series HANDLING DEVICES MB91301 series * Operation at start-up Always apply a settings initialization (INIT) to the INIT pin immediately after turning on the power. Also, in order to provide a delay while the oscillator circuits stabilize immediately after start-up, maintain the "L" level input to the INIT pin for the required stabilization delay time. (The initialization processing (INIT) triggered by the INIT pin initializes the oscillation stabilization delay time to the minimum setting.) * External clock input at start-up At power-on start-up, always input a clock signal until the oscillation stabilization delay time is ended. * Output indeterminate at power-on time When the power is turned on, the output pin may remain indeterminate until the internal power supply becomes stable. * Built-in DC/DC regulator This device has a built-in regulator, requiring 3.3 V input to the Vcc pin and a bypass capacitor of approximately 4.7 F connected to the C pin for the regulator. 3.3 V VCC AVCC AVRH 0.05 F AVR AVSS/AVRL VSS MB91301 series VSS 4.7 F C GND Note of built-in DC/DC regulator * Note on use of the A/D converter As the MB91301 series contains an A/D converter, be sure to supply power to AVcc at 3.3 V and insert a capacitor of at least 0.05 F between the AVR pin and the AVss/AVRL pin. 3.3 V AVCC AVRH AVR 0.05 F AVSS/AVRL MB91301 series Note on Use of A/D Converter 22 MB91301 Series * Preventing Latchup When CMOS integrated circuit devices are subjected to applied voltages higher than VCC at input and output pins, or to voltages lower than VSS, as well as when voltages in excess of rated levels are applied between VCC and VSS, a phenomenon known as latchup can occur. When a latchup condition occurs, the supply current can increase dramatically and may destroy semiconductor elements. In using semiconductor devices, always take sufficient care to avoid exceeding maximum ratings. * Power supply pins Devices with multiple VCC and VSS supply pins are designed to prevent problems such as latchup occurring by providing internal connections between pins at the same potential. However, in order to reduce unwanted radiation, prevent abnormal operation of strobe signals due to a rise in ground level, and to maintain the total output current ratings, all such pins should always be connected externally to power supply or ground. Also, ensure that the impedance of the VCC and VSS connections to the power supply are as low as possible. In addition, it is recommended that a bypass capacitor of approximately 0.1F be connected between VCC and VSS. Connect the capacitor close to the VCC and VSS pins. * Crystal oscillators Noise in proximity to the X0 and X1 pins can cause abnormal operation in this device. Printed circuit boards should be designed so that the X0 and X1 pins, crystal (or ceramic) oscillator, and bypass capacitor connected to ground are placed as close together as possible. Also, to ensure stable operation, it is strongly recommended that the printed circuit board art work be designed such that the X0 and X1 pins are surrounded by ground. Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device. * Treatment of NC and OPEN pins Pins marked as "NC" or "OPEN" must be left open-circuit. * Treatment of unused input pins If unused input pins are left open, abnormal operation may result. Any unused input pins should be connected to pull-up or pull-down resistors. * Mode pins (MD0 to MD2) These pins should be connected directly to VCC or VSS. To prevent the device erroneously switching to test mode due to noise, design the printed circuit board such that the distance between the mode pins and VCC or VSS is as short as possible and the connection impedance is low. * Remarks for External Clock Operation When external clock is selected, supply it to X0 pin generally, and simultaneously the opposite phase clock to X0 must be supplied to X1 pin. However, in this case the stop mode must not be used (because X1 pin stops at "H" output in stop mode) . When operating at 12.5 MHz or less, the microcontroller can be used with the clock signal supplied only to pin X0. "Using an external clock (normal) and (12.5 MHz) " shows examples of how the MB91301 uses the external clock. 23 MB91301 Series X0 X1 MB91301 series Note: Stop mode (oscillation stop mode) can not be used. Using an external clock (normal) X0 OPEN X1 MB91301 series Using an external clock (12.5 MHz Max) * Notes on during operation of PLL clock mode If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even when there is no external oscillator or external clock input is stopped. Performance of this operation, however, cannot be guaranteed. * Clock control block For L-level input to the INIT pin, allow for the regulator settling time or oscillation settling time. * Bit search module The 0-detection, 1-detection, and transition-detection data registers (BSD0, BSD1, and BSDC) are only wordaccessible. * I/O port access Byte access only for access to port * Shared port function switching To switch a pin that also serves as a port, use the port function register (PFR). Note, however, that bus pins are switched depending on external bus settings. * D-bus memory Do not set a code area in D-bus memory. No instruction fetch is performed to the D-bus. Instruction fetches to the D-bus area result in incorrect data interpreted as code, which can cause the microcontroller to lose control. Do not set a data area in I-bus memory. 24 MB91301 Series * I-bus memory Do not set a stack area or vector table in I-bus memory. It may cause a hang during EIT processing (including RETI). Recovery from the hang requires a reset. Do not perform DMA transfer to I-bus memory. * Low-power consumption modes * To enter the standby mode, use the synchronous standby mode (set with the SYNCS bit as bit 8 in the TBCR, or time-base counter control register) and be sure to use the following sequence: (LDI #value_of_standby, R0) (LDI #_STCR, R12) STB R0, @R12 ; Write to standby control register (STCR) LDUB @R12, R0 ; Read STCR for synchronous standby LDUB @R12, R0 ; Read STCR again for dummy read NOP ; NOP x 5 for timing adjustment NOP NOP NOP NOP * If you use the monitor debugger, follow the precautions below: Do not set a breakpoint within the above array of instructions. Do not single-step the above array of instructions. * Prefetch When accessing a prefetch-enabled little endian area, use word access only (access in 32 bits). Byte or halfword access results in wrong data read. * MCLK and SYSCLK MCLK causes a stop in SLEEP/STOP mode while SYSCLK causes a stop only in STOP mode. Use either depending on each application. * Pull-up control When function pins listed in the AC specifications (such as external bus control pins) have pull-up control, enabling the pull-up resistor for a pin causes the actual pin load conditions to change. As all AC specifications for this device were measured under the condition of pull-up resistors disabled, the values are not guaranteed of AC specifications when pull-up resistors are enabled. Even if the pull-up resistor is set to enabled for a pin, if the HIZ bit in the standby control register (STCR) specifies setting output pins to high impedance during stop mode (HIZ = 1) , changing to stop mode (STOP = 1) causes the pull-up resistor to be disabled. 25 MB91301 Series * R15 (General purpose register) When any of the following instructions is executed, the SSP* or USP* value is not used as R15, resulting in an incorrect value written to memory. AND R15, @Ri ANDH R15, @Ri ANDB R15, @Ri OR R15, @Ri ORH R15, @Ri ORB R15, @Ri EOR R15, @Ri EORH R15, @Ri EORB R15, @Ri XCHB @Rj, R15 * : R15 is a virtual register. When a program attempts to access R15, the SSP or USP is accessed depending on the status of the "S" flag as an SP flag. When coding the above ten instructions using an assembler, specify a general-purpose register other than R15. * RETI instruction Please do not neither control register of the instruction cache nor the data access to RAM of the instruction cache immediately before the instruction of RETI. * Notes on the PS register Since some instructions manipulate the PS register earlier, the following exceptions may cause the interrupt handler to break or the PS flag to update its display setting when the debugger is being used. As the microcontroller is designed to carry out reprocessing correctly upon returning from such an EIT event, it performs operations before and after the EIT as specified in either case. * The following operations may be performed when the instruction immediately followed by a DIVOU/DIVOS instruction is (a) halted by a user interrupt or NMI, (b) single-stepped, or (c) breaks in response to a data event or emulator menu: (1) D0 and D1 flags are updated earlier. (2) The EIT handler (user interrupt/NMI or emulator) is executed. (3) Upon returning from the EIT, the DIVOU/DIVOS instruction is executed and the D0 and D1 flags are updated to the same values as those in (1) above. * The following operations are performed when the ORCCR/STILM/MOV Ri and PS instructions are executed to enable interruptions when a user interrupt or NMI trigger event has occurred. (1) The PS register is updated earlier. (2) The EIT handler (user interrupt/NMI or emulator) is executed. (3) Upon returning from the EIT, the above instructions are executed and the PS register is updated to the same value as that in (1) above. * A/D converter When the device is turned on or returns from a reset or stop, it takes time for the external capacitor to be charged, requiring the A/D converter to wait for at least 10 ms. * Watchdog timer The watchdog timer function of this model monitors that a program delays a reset within a certain period of time and resets the CPU if the program fails to delay it, for example, because the program runs out of control. Once the watchdog timer function is enabled, therefore, the watchdog timer continues to operate until a reset takes place. An exception, for example during stop, sleep and DMA transfer modes, is the automatic delaying of a reset under a condition in which the CPU stops program execution. Note, however, that a watchdog reset may not occur in the above state caused when the system runs out of control. If this is the case, use the external INIT pin to cause a reset (INIT) . 26 MB91301 Series Unique to the evaluation chip MB91V301A * Tool reset On an evaluation board, use the chip with INIT and TRST connected together. * Simultaneous occurrences of a software break and a user interrupt/NMI When a software break and a user interrupt /NMI take place at the same time, the emulator debugger can cause the following phenomena: * The debugger stops pointing to a location other than the programmed breakpoints. * The halted program is not re-executed correctly. If these phenomena occur, use a hardware break instead of the software break. If the monitor debugger has been used, avoid setting any break at the relevant location. * Single-stepping the RETI instruction If an interrupt occurs frequently during single stepping, execute only the relevant processing routine repeatedly after single-stepping RETI. This will prevent the main routine and low-interrupt-level programs from being executed. Do not single-step the RETI instruction for avoidance purposes. When the debugging of the relevant interrupt routine becomes unnecessary, perform debugging with that interrupt disabled. * Operand break A stack pointer placed in an area set for a DSU operand break can cause a malfunction. Do not apply a data event break to access to the area containing the address of a system stack pointer. * ICE startup sequence When using the ICE, when you start debugging, ensure that the bus configuration is set correctly for the area being used before downloading. After turning on the power to the target, the states of the RD and WR0 to WR3 pins are undefined until you perform the above setting. Accordingly, include enabling pull-up as part of the startup sequence. If using these pins as general-purpose ports, set as output ports to prevent conflict with the output signals during the time the pin states are undefined. External bus width Pin name RD WR0 WR1 (P85) WR2 (P86) WR3 (P87) * : Use as output ports. 32 bit Pull-up Pull-up Pull-up Pull-up Pull-up 16 bit Pull-up Pull-up Pull-up * * 8 bit Pull-up Pull-up * * * 27 MB91301 Series * Configuration batch file The example batch file below sets the mode vector and sets up the CS0 configuration register for the download area. Use values appropriate to the hardware in the wait, timing, and other settings. #--------------------------------------------------------# Set MODR (0x7fd) =Enable In memory+16 bit External Bus set mem/byte 0x7fd=0x5 #--------------------------------------------------------# Set ASR0 (0x640) ; 0x0010_0000 - 0x002f_ffff set mem/halfword 0x640=0x0010 #--------------------------------------------------------# Set ACR0 (0x642) # ; ASZ [3:0]=0101:2 Mbytes # ; DBW [1:0]=01:16 bit width, automatically set from MODR # ; BST [1:0]=00:1 burst (16 bit x 2) # ; SREN=0:Disable BRQ # ; PFEN=1:Enable Pre fetch buffer # ; WREN=1:Enable Write operation # ; LEND=0: Big endian # ; TYPE [3:0]=0010:WEX: Disable RDY set mem/harfword 0x642=0x5462 #--------------------------------------------------------# Set AWR0 (0x660) # ; W15-12=0010:auto wait=2 # ; WR07, 06=01:RD, WR delay=1cycle # ; W05, 04=01:WR->WR delay=1cycle (for WEX) # ; W03 =1:MCLK->RD/WR delay=0.5cycle # ; :for async Memory # ; W02 =0:ADR->CS delay=0 # ; W01 =0:ADR->RD/WR setup 0cycle # ; W00 =RD/WR->ADR hold 0cycle set mem/halfword 0x660=0x2058 #--------------------------------------------------------* Emulation memory If SRAM as the emulation memory is built on target board, SRAM for be accessed by RD, WR signal, and +BYTE control signal can not be used. (The external bus is initialized to the bus mode for accessing RD, WRn after reset.) 28 MB91301 Series BLOCK DIAGRAM * MB91302A, MB91V301A FR CPU Core 32 32 Instruction Cache 4 KB DREQ0, DREQ1 DACK0, DACK1 DEOP0, DEOP1 IOWR IORD Bit search module MB91302A : RAM 4 KB MB91V301A : RAM 8 KB (stack) DMAC 5 channels MB91302A : ROM 4 KB* MB91V301A : RAM 8 KB 32 Bus Converter 32 X0, X1 MD0 to MD2 INIT 16 32 Adapter Clock control 16 External memory I/F A23 to A00 D31 to D16 D15 to D00 RD, WR WR0 to WR3 CS0 to CS7 RDY BRQ BGRNT SYSCLK MCLK AS MCLKE SRAS SCAS SWE DQMUU, L DQMLU,L LBA BAA PPG0 to PPG3 TRG0 to TRG3 Interrupt controller INT0 to INT7 NMI SIN0 to SIN2 SOT0 to SOT2 SCK0 to SCK2 8 channels External interrupts SDRAM I/F 3 channels UART 4 channels PPG timer 3 channels U-TIMER PORT I/F AN0 to AN3 ATG AVRH, AVCC AVSS/AVRL TIN0 to TIN2 PORT 4 channels A/D converter 3 channels Reload timer 2 channels I2C I/F SDA0, SDA1 SCL0, SCL1 Free Run Timer FRCK 4 channels Input Capture ICU0 to ICU3 * : ROM has non-ROM model, the optimal real time OS internal model, and the IPL (Internal Program Loader) internal model by adding the user ROM model. 29 MB91301 Series CPU 1. Memory Space The FR family has 4 Gbytes (232 addresses) of logical address space with linear access from the CPU. * Direct Addressing Areas The following areas of address space are used for I/O operations. These areas are called direct addressing areas, in which the address of an operand can be specified directly during an instruction. The direct areas differ according to the size of the data accessed, as follows. byte data access : 000H to 0FFH half word data access : 000H to 1FFH word data access : 000H to 3FFH 30 MB91301 Series * Memory map (MB91302A) (Single chip mode) (MB91302A) Internal ROM External bus mode (MB91302A) External ROM External bus mode (MB91V301A) Internal ROM External bus mode (MODR register at ROAM = 1) (MB91V301A) External ROM External bus mode 0000 0000H I/O Direct addre ssing area see "I/O MAP" I/O 1 I/O Direct addre ssing area see "I/O MAP" I/O 1 I/O Direct addre ssing area see "I/O MAP" I/O 1 I/O Direct addre ssing area see "I/O MAP" I/O 1 I/O Direct addre ssing area see "I/O MAP" I/O 1 0000 0400H I/O 0001 0000H 0002 0000H I/O I/O I/O I/O I-RAM I-RAM I-RAM I-RAM I-RAM 0003 E000H Access prohibited Internal RAM 4 Kbytes Access prohibited Internal RAM 4 Kbytes Access prohibited Internal RAM 4 Kbytes Access prohibited Access prohibited 0003 F000H Internal RAM 8 Kbytes Internal RAM 8 Kbytes Access prohibited Internal RAM 8 Kbytes 0004 0000H 0004 2000H External area 0006 0000H 000E 0000H Access prohibited Access prohibited External area External area External area 000F E000H 000F F000H Internal ROM 4 Kbytes*2 0010 0000H Internal ROM 4 Kbytes*2 Internal RAM 8 Kbytes emulation Access prohibited FFFF FFFFH External area External area External area External area MB91302A has non-ROM model, the optimal real time OS internal model, and the IPL (Internal program Loader) internal model by adding the user ROM model. *1 : On specific area between 10000H and 2000H, 4 Kbytes RAM can be used. Refer to "INSTRUCTION CACHE". *2 : The real time OS internal model stores the real time OS kernel. The program loader internal model stores the program loader. Note : Internal ROM emulation : only MB91V301A Note : Each mode is set depending on the mode vector fetch after INIT is negated. (For mode setting, see "MODE SETTINGS".) 31 MB91301 Series 2. Registers The FR series has two types of registers: application-specific registers in the CPU and general purpose registers in memory. * Dedicated registers Program counter (PC) Program status (PS) Table base register (TBR) Return pointer (RP) System stack pointer (SSP) User stack pointer (USP) Multiplication and division result register (MDH/MDL) : 32-bit register. Stores the current instruction address. : 32-bit register. Contains the register pointer and condition code. : Stores the top address of the vector table used by the EIT (exception/interrupt/ trap) function. : Stores the subroutine return address. : Points to the system stack area. : Points to the user stack area. : 32-bit registers used for multiplication and division. 32 bit PC Initial value Program counter Program status Table base register Return pointer System stack pointer User stack pointer Multiplication and division result register 000F FC00H XXXX XXXXH 0000 0000H XXXX XXXXH XXXX XXXXH XXXX XXXXH XXXX XXXXH PS TBR RP SSP USP MDH MDL * PC (Program Counter) The PC is the program counter and stores the address of the currently executing instruction. 31 PC 0 PC * Table base register (TBR) The TBR is the table base register and stores the top address of the vector table used by the EIT function. 31 TBR 0 TBR 32 MB91301 Series * Return pointer (RP) The RP is the return pointer and stores the subroutine return address. 31 RP 0 RP * System stack pointer (SSP) The SSP is the system stack pointer and functions as R15 when the S flag is "0". 31 SSP 0 SSP * User stack pointer (USP) The USP is the user stack pointer and functions as R15 when the S flag is "1". 31 USP 0 USP * Multiplication and division result register (MDH/MDL) MDH/MDL : 32-bit registers used for multiplication and division. MDH MDL : Remainder : Quotient 31 MDH MDL 0 Multiplication and division result register 33 MB91301 Series * Program status (PS) This register holds the program status and is divided into the ILM, SCR, and CCR. Bit position 31 20 16 10 87 0 ILM SCR CCR PS * Condition code register (CCR) S flag : Specifies which stack pointer to use as R15. I flag : Enables or disables user interrupt requests. N flag : Indicates the sign when an operation result is represented as a "2" complement integer. Z flag : Indicates whether an operation result is "0". V flag : Indicates whether an overflow occurred for an operation result when the operation operand is represented as a "2" complement integer. C flag : Indicates whether an operation resulted in a borrow or a carry from the most significant bit. 7 6 5 S 4 I 3 N 2 Z 1 V 0 C Initial Value - - 00XXXXB CCR * System condition code register (SCR) D1, D0 flags : Stores intermediate data for stepwise multiplication operations. T flags : A flag specifying whether the step trace trap function is enabled or not. 10 D1 9 D0 8 T Initial Value XX0B SCR * Interrupt level mask register(ILM) ILM4 to ILM0 : This register stores the interrupt level mask value. The value in the ILM register is used as the level mask. Only interrupt requests to the CPU that have an interrupt level that is higher than the level specified in ILM are accepted. 20 ILM4 0 0 1 19 ILM3 0 1 1 18 ILM2 0 *** 0 *** 1 1 ILM 34 1 0 0 17 ILM1 0 16 ILM0 0 Interrupt Level 0 *** 15 *** 31 High (Medium) Low Initial Value 01111B MB91301 Series GENERAL PURPOSE REGISTERS General purpose registers R0 to R15 are used by the CPU. The registers are used as the accumulator and memory access pointers for CPU operations. 32-bit R0 R1 Initial Value XXXX XXXXH R12 R13 R14 R15 AC (Accumulator) FP (Frame Pointer) SP (Stack Pointer) XXXX XXXXH 0000 0000H The following three registers are treated as having special meanings to enhance the operation of some instructions. R13 : Virtual accumulator (AC) R14 : Frame pointer (FP) R15 : Stack pointer (SP) The values of R0 to R14 after a reset are undefined. R15 is initialized to 0000 0000H (SSP value) . 35 MB91301 Series MODE SETTINGS In the FR series, the mode is set by the mode pins (MD2, MD1, and MD0) and mode register (MODR). 1. Mode Pins The MD2, MD1, and MD0 pins specify how the mode vector fetch is performed. Mode Pins Reset vector access Mode name area MD2 MD1 MD0 0 0 0 0 0 1 Internal ROM vector mode External ROM vector mode Internal External Remarks Single-chip mode* The bus width is specified by the mode register. Values other than those listed in the table are prohibited. * : Single chip mode is able to set only MB91302A. 2. Mode Register (MODR) * Details of mode register (MODR) The data written to the mode register by the mode vector fetch operation (see "3.11.3 reset sequences") is called the mode data. After the data is set to the mode register (MODR), the device operates with the operating mode specified by this data. The mode register is set by all types of reset. The register cannot be written to by user programs. <Details of mode register (MODR) > Operation mode setting bits Initial Value bit Address 23 22 21 20 19 18 ROMA W 17 WTH1 W 16 WTH0 W XXXXXXXXB <Details of mode data> Operation mode setting bits Initial Value bit Address 31 30 29 28 27 26 ROMA W 25 WTH1 W 24 WTH0 W XXXXXXXXB Bit31 to bit24 are all reserved bits. Be sure to set this bit to "00000." Operation is not guaranteed when any value other than "00000." is set. 36 MB91301 Series * Operating mode Bus mode Single chip Internal ROM external bus External ROM external bus Access mode 32-bit bus width 16-bit bus width 8-bit bus width * Bus mode The bus mode controls the operations of internal ROM and the external access function. It is specified with the mode setting pins (MD2, MD1, and MD0) and the ROMA bit in mode data. * Access mode The access mode controls the external data bus width. It is specified with the WTH1 and WTH0 bits in the mode register and the DBW1 and DBW0 bits in area configuration registers 0 to 7 (ACR0 to ACR7). * Bus Modes The FR family has three bus modes: bus mode 0 (single-chip mode), bus mode 1 (internal-ROM, external-bus mode), and bus mode 2 (external-ROM, external-bus mode). The MB91V301A supports only bus mode 2 (external-ROM, external-bus mode). See "1. Memory Space" in CPU for details. * Bus mode0 (single chip mode) (only MB91302A) The internal I/O, 4 Kbytes D-bus RAM, 32 Kbytes F-bus RAM (FRAM) and 96 Kbytes F-bus ROM are valid, while access to any other areas is invalid under this mode. The function of external pin is peripheral or generalpurpose port. The pin can not be used as the bus pin. * Bus mode 1 (internal ROM external bus mode) The internal I/O, D-bus RAM, F-bus RAM (FRAM) and F-bus ROM are valid, and access to areas where external access is enabled will access external space under this mode. A part of an external terminal functions as a bus terminal. * Bus mode 2 (External-ROM, external-bus mode) This mode enables internal I/O and D-bus RAM, in which any access is access to external space. Some external pins serve as bus pins. 37 MB91301 Series I/O MAP This shows the location of the various peripheral resource registers in the memory space. [How to read the table] Address 000000H Register +0 +1 +2 +3 PDR0 [R/W] B PDR1 [R/W] B PDR2 [R/W] B PDR3 [R/W] B XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Block T-unit Port Data Register Read/write attribute, Access type (B : Byte, H : Half-word, W : Word) Initial value after a reset Register name (Address of column 1 register is 4n, address of column 2 register is 4n+2, etc.) Location of left-most register (When using word access, the register in column 1 is in the MSB side of the data.) Note : Initial values of register bits are represented as follows : "1" : Initial value"1" "0" : Initial value"0" "X" : Initial value"X" "-" : No physical register at this location 38 MB91301 Series Address 000000H 000004H 000008H 00000CH 000010H 000014H to 00003CH 000040H 000044H 000048H 00004CH 000050H 000054H 000058H 00005CH Register +0 PDR0 [R/W] B XXXXXXXX PDR8 [R/W] B XXXXXXXX +1 PDR1 [R/W] B XXXXXXXX PDR9 [R/W] B - XXXXXXX PDRG [R/W] B XXXXXXXX PDRH [R/W] B - - - - - XXX EIRR [R/W] B, H, W ENIR [R/W] B, H, W 00000000 00000000 DICR [R/W] B, H, W HRCL [R/W] B, H, W -------0 0 - - 11111 TMRLR0 [W] H, W XXXXXXXX XXXXXXXX TMRLR1 [W] H, W XXXXXXXX XXXXXXXX TMRLR2 [W] H, W XXXXXXXX XXXXXXXX ELVR [R/W] B, H, W 00000000 TMR0 [R] H, W XXXXXXXX XXXXXXXX TMCSR0 [R/W] B, H, W - - XX0000 00000000 TMR1 [R] H, W XXXXXXXX XXXXXXXX TMCSR1 [R/W] B, H, W - - XX0000 00000000 TMR2 [R] H, W XXXXXXXX XXXXXXXX TMCSR2 [R/W] B, H, W - - XX0000 00000000 PDRJ [R/W] B XXXXXXXX +2 PDR2 [R/W] B XXXXXXXX PDR6 [R/W] B XXXXXXXX PDRA [R/W] B XXXXXXXX +3 PDRB [R/W] B XXXXXXXX Block T-unit Port Data Register R-bus Port Data Register Reserved Ext int DLYI/I-unit Reload Timer 0 Reload Timer 1 Reload Timer 2 000060H SIDR0 [R] SSR0 [R/W] B, H, W SCR0 [R/W] B, H, W SMR0 [R/W] B, H, W SODR0 [W] B, H, W 00001000 00000100 00 - - 0 - 0 XXXXXXXX UTIM0 [R] H, W (UTIMR0 [W] H, W) 00000000 00000000 DRCL0 [W] B -------UTIMC0 [R/W] B 0 - - 00001 UART0 000064H U-TIMER 0 000068H SIDR1 [R] SSR1 [R/W] B, H, W SCR1 [R/W] B, H, W SMR1 [R/W] B, H, W SODR1 [W] B, H, W 00001000 00000100 00 - - 0 - 0 XXXXXXXX UTIM1 [R] H, W (UTIMR1 [W] H, W ) 00000000 00000000 DRCL1 [W] B -------UTIMC1 [R/W] B 0 - - 00001 UART1 00006CH U-TIMER 1 (Continued) 39 MB91301 Series Address Register +0 +1 +2 +3 SIDR2 [R] SSR2 [R/W] B, H, W SCR2 [R/W] B, H, W SMR2 [R/W] B, H, W SODR2 [W] B, H, W 00001000 00000100 00 - - 0 - 0 XXXXXXXX UTIM2 [R] H, W (UTIMR2 [W] H, W ) 00000000 00000000 ADCR [R] B, H, W 000000XX XXXXXXXX ADCR0 [R] B, H, W XXXXXXXX ADCR1 [R] B, H, W XXXXXXXX IBCR0 [R/W] B, H, W 00000000 IBSR0 [R] B, H, W 00000000 ITBA0 [R, R/W] B, H, W 00000000 00000000 ISMK0 [R/W] B, H, W 01111111 ICCR0 [R, W, R/W] B, H, W 00011111 IBCR1 [R/W] B, H, W 00000000 IBSR1 [R] B, H, W 00000000 ITBA1 [R, R/W] B, H, W 00000000 00000000 ISMK1 [R/W] B, H, W 01111111 ICCR1 [R, W, R/W] B, H, W 00011111 ISBA1 [R, R/W] B, H, W 00000000 IDBL1 [R, R/W] B, H, W 00000000 ISBA0 [R, R/W] B, H, W 00000000 IDBL0 [R, R/W] B, H, W 00000000 DRCL2 [W] B -------UTIMC2 [R/W] B 0 - - 00001 Block 000070H UART2 000074H 000078H 00007CH 000080H to 000090H 000094H U-TIMER 2 ADCS [R/W] B, H, W 00000000 00000000 ADCR2 [R] B, H, W XXXXXXXX A/D Converter ADCR3 [R] B, H, W Sequential Comparator XXXXXXXX Reserved 000098H ITMK0 [R, R/W] B, H, W 00111111 11111111 IDAR0 [R/W] B, H, W 00000000 I2C interface0 00009CH 0000A0H 0000A4H 0000A8H to 0000B0H 0000B4H Reserved Reserved 0000B8H ITMK1 [R, R/W] B, H, W 00111111 11111111 IDAR1 [R/W] B, H, W 00000000 I2C interface1 0000BCH 0000C0H 0000C4H 0000C8H to 0000D0H 0000D4H 0000D8H Reserved TCCS [R/W] B, H, W 16 bit Free 00000000 Run Timer 16 bit Input Capture (Continued) TCDT [R/W] H, W 00000000 00000000 IPCP1 [R/W] H, W XXXXXXXX_XXXXXXXX IPCP0 [R/W] H, W XXXXXXXX_XXXXXXXX 40 MB91301 Series Address 0000DCH 0000E0H 0000E4H to 000114H 000118H 000011CH 000120H 000124H 000128H 00012CH 000130H 000134H 000138H 00013CH 000140H to 0001FCH 000200H 000204H 000208H 00020CH 000210H Register +0 +1 +2 +3 IPCP3 [R/W] H, W XXXXXXXX_XXXXXXXX ICS23 [R/W] B, H, W 00000000 GCN10 [R/W] H 00110010 00010000 PTMR0 [R] H 11111111 11111111 PDUT0 [W] H, W XXXXXXXX XXXXXXXX PTMR1[R] H 11111111 11111111 PDUT1 [W] H, W XXXXXXXX XXXXXXXX PTMR2 [R] H 11111111 11111111 PDUT2 [W] H, W XXXXXXXX XXXXXXXX PTMR3[R] H 11111111 11111111 PDUT3 [W] H, W XXXXXXXX XXXXXXXX DMACA0 [R/W] B, H, W*1 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB0 [R/W] B, H, W 00000000 00000000 XXXXXXXX XXXXXXXX DMACA1 [R/W] B, H, W*1 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB1 [R/W] B, H, W 00000000 00000000 XXXXXXXX XXXXXXXX DMACA2 [R/W] B, H, W*1 00000000 0000XXXX XXXXXXXX XXXXXXXX PCSR0 [W] H, W XXXXXXXX XXXXXXXX PCNH0 [R/W] B 00000000 PCNL0 [R/W] B 000000X0 GCN20 [R/W] B 00000000 IPCP2 [R/W] H, W XXXXXXXX_XXXXXXXX ICS01 [R/W] B, H, W 00000000 Block 16 bit Input capture Reserved PPG timer Reserved PPG0 PCSR1 [W] H, W XXXXXXXX XXXXXXXX PCNH1 [R/W] B 00000000 PCNL1 [R/W] B 000000X0 PPG1 PCSR2 [W] H, W XXXXXXXX XXXXXXXX PCNH2 [R/W] B 00000000 PCNL2 [R/W] B 000000X0 PPG2 PCSR3 [W] H, W XXXXXXXX XXXXXXXX PCNH3 [R/W] B 00000000 PCNL3 [R/W] B 000000X0 PPG3 Reserved DMAC (Continued) 41 MB91301 Series Address 000214H 000218H 00021CH 000220H 000224H 000228H to 00023CH 000240H 000244H to 000300H 000304H 000308H to 0003E0H 0003E4H 0003E8H to 0003EFH 0003F0H 0003F4H 0003F8H 0003FCH Register +0 +1 +2 +3 DMACB2 [R/W] B, H, W 00000000 00000000 XXXXXXXX XXXXXXXX DMACA3 [R/W] B, H, W*1 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB3 [R/W] B, H, W 00000000 00000000 XXXXXXXX XXXXXXXX DMACA4 [R/W] B, H, W*1 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB4 [R/W] B, H, W 00000000 00000000 XXXXXXXX XXXXXXXX DMACR [R/W] B 0XX00000 XXXXXXXX XXXXXXXX XXXXXXXX BSD0 [W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSD1 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSDC [W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSRR [R] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DDRG [R/W] B 00000000 DDRH [R/W] B - - - - - 000 DDRJ [R/W] B 00000000 ICHCR [R/W] B, H, W 0 - 000000 ISIZE [R/W] B, H, W - - - - - - 10 Block DMAC Reserved DMAC Reserved I-Cache Reserved I-Cache Reserved Bit Search Module 000400H R-bus Data Direction Register (Continued) 42 MB91301 Series Address 000404H to 00040CH 000410H 000414H to 00041CH Register +0 +1 PFRG [R/W] B 00 - - - - - PFRH [R/W] B ------0 PFRJ [R/W] B - 000 - 00 +2 +3 Block Reserved R-bus Port Function Register Reserved R-bus Pull-up Resistance Control Register Reserved 000420H PCRH [R/W] B - - - - - 000 000424H to 00043CH 000440H 000444H 000448H 00044CH 000450H 000454H 000458H 00045CH 000460H 000464H 000468H ICR00 [R/W] B, H, W ICR01 [R/W] B, H, W ICR02 [R/W] B, H, W ICR03 [R/W] B, H, W - - - 11111 - - - 11111 - - - 11111 - - - 11111 ICR04 [R/W] B, H, W ICR05 [R/W] B, H, W ICR06 [R/W] B, H, W ICR07 [R/W] B, H, W - - - 11111 - - - 11111 - - - 11111 - - - 11111 ICR08 [R/W] B, H, W ICR09 [R/W] B, H, W ICR10 [R/W] B, H, W ICR11 [R/W] B, H, W - - - 11111 - - - 11111 - - - 11111 - - - 11111 ICR12 [R/W] B, H, W ICR13 [R/W] B, H, W ICR14 [R/W] B, H, W ICR15 [R/W] B, H, W - - - 11111 - - - 11111 - - - 11111 - - - 11111 ICR16 [R/W] B, H, W ICR17 [R/W] B, H, W ICR18 [R/W] B, H, W ICR19 [R/W] B, H, W - - - 11111 - - - 11111 - - - 11111 - - - 11111 ICR20 [R/W] B, H, W ICR21 [R/W] B, H, W ICR22 [R/W] B, H, W ICR23 [R/W] B, H, W - - - 11111 - - - 11111 - - - 11111 - - - 11111 ICR24 [R/W] B, H, W ICR25 [R/W] B, H, W ICR26 [R/W] B, H, W ICR27 [R/W] B, H, W - - - 11111 - - - 11111 - - - 11111 - - - 11111 ICR28 [R/W] B, H, W ICR29 [R/W] B, H, W ICR30 [R/W] B, H, W ICR31 [R/W] B, H, W - - - 11111 - - - 11111 - - - 11111 - - - 11111 ICR32 [R/W] B, H, W ICR33 [R/W] B, H, W ICR34 [R/W] B, H, W ICR35 [R/W] B, H, W - - - 11111 - - - 11111 - - - 11111 - - - 11111 ICR36 [R/W] B, H, W ICR37 [R/W] B, H, W ICR38 [R/W] B, H, W ICR39 [R/W] B, H, W - - - 11111 - - - 11111 - - - 11111 - - - 11111 ICR40 [R/W] B, H, W ICR41 [R/W] B, H, W ICR42 [R/W] B, H, W ICR43 [R/W] B, H, W - - - 11111 - - - 11111 - - - 11111 - - - 11111 Interrupt Controller (Continued) 43 MB91301 Series Address 00046CH 000470H to 00047CH Register +0 +1 +2 +3 ICR44 [R/W] B, H, W ICR45 [R/W] B, H, W ICR46 [R/W] B, H, W ICR47 [R/W] B, H, W - - - 11111 - - - 11111 - - - 11111 - - - 11111 RSRR [R, R/W] B, H, W 10000000 (INIT) - 0 - XX - 00 (INIT) XXX - - X00 (RST) CLKR [R/W] B, H, W - 000 - 000 (INIT) - XXX - XXX (RST) STCR [R/W] B, H, W TBCR [R/W] B, H, W 001100 - 1 (INIT) 00XXX - 00 (INIT) 0011XX - 1 (INIT) 00XXX - XX (RST) 00X1XX - X (RST) WPR [W] B, H, W XXXXXXXX (INIT) XXXXXXXX (RST) Block Interrupt Controller 000480H CTBR [W] B, H, W XXXXXXXX (INIT) XXXXXXXX (RST) 000484H 000488H to 0005FCH 000600H 000604H 000608H 00060CH 000610H 000614H 000618H 00061CH 000620H 000624H 000628H 00062CH DIVR0 [R/W] B, H, W DIVR1 [R/W] B, H, W 00000011 (INIT) 0000 - - - - (INIT) XXXX - - - - (RST) XXXXXXXX (RST) Clock Control unit Reserved DDR2 [R/W] B 00000000 DDR6 [R/W] B 00000000 DDRB [R/W] B 00000000 T-unit Data Direction Register DDR0 [R/W] B 00000000 DDR8 [R/W] B 00000000 DDR1 [R/W] B 00000000 DDR9 [R/W] B - 0000000 DDRA [R/W] B 00000000 PFR8 [R/W] B 111 - - 0 - PFRB2 [R/W] B 000 - - - 00 PCR0 [R/W] B 00000000 PCR8 [R/W] B 00000000 PFR9 [R/W] B - 0000111 PCR1 [R/W] B 00000000 PFR6 [R/W] B 11111111 PFRA1 [R/W] B 11111111 PFRA2 [R/W] B --0----PCR2 [R/W] B 00000000 PCR6 [R/W] B 00000000 PFR61 [R/W] B - - - - 0000 PFRB1 [R/W] B 00000000 PCRB [R/W] B 00000000 T-unit Port Function Register PCR9 [R/W] B - 000 - - 0 PCRA [R/W] B 00000000 T-unit Pull-up Resistance Control Register (Continued) 44 MB91301 Series Address 000630H to 00063CH 000640H 000644H 000648H 00064CH 000650H 000654H 000658H 00065CH 000660H 000664H 000668H 00066CH 000670H 000674H 000678H 00067CH 000680H Register +0 +1 ASR0 [R/W] H, W 00000000 00000000 ASR1 [R/W] H, W XXXXXXXX XXXXXXXX ASR2 [R/W] H, W XXXXXXXX XXXXXXXX ASR3 [R/W] H, W XXXXXXXX XXXXXXXX ASR4 [R/W] H, W XXXXXXXX XXXXXXXX ASR5 [R/W] H, W XXXXXXXX XXXXXXXX ASR6 [R/W] H, W XXXXXXXX XXXXXXXX ASR7 [R/W] H, W XXXXXXXX XXXXXXXX AWR0 [R/W] B, H, W 01111111 11111011 AWR2 [R/W] B, H, W XXXXXXXX XXXXXXXX AWR4 [R/W] B, H, W XXXXXXXX XXXXXXXX AWR6 [R/W] B, H, W XXXXXXXX XXXXXXXX MCRA [R/W] B, H, W MCRB [R/W] B, H, W XXXXXXXX XXXXXXXX IOWR0 [R/W] B, H, W IOWR1 [R/W] B, H, W IOWR2 [R/W] B, H, W XXXXXXXX XXXXXXXX XXXXXXXX CSER [R/W] B, H, W CHER [R/W] B, H, W 00000001 11111111 RCR [R/W] B, H, W 00XXXXXX XXXX0XXX TCR [R/W] B, H, W 00000000 (INIT) 0000XXXX (RST) ACR0 [R/W] H, W 1111XX00 00000000 ACR1 [R/W] B, H, W XXXXXXXX XXXXXXXX ACR2 [R/W] B, H, W XXXXXXXX XXXXXXXX ACR3 [R/W] B, H, W XXXXXXXX XXXXXXXX ACR4 [R/W] B, H, W XXXXXXXX XXXXXXXX ACR5 [R/W] B, H, W XXXXXXXX XXXXXXXX ACR6 [R/W] B, H, W XXXXXXXX XXXXXXXX ACR7 [R/W] B, H, W XXXXXXXX XXXXXXXX AWR1 [R/W] B, H, W XXXXXXXX XXXXXXXX AWR3 [R/W] B, H, W XXXXXXXX XXXXXXXX AWR5 [R/W] B, H, W XXXXXXXX XXXXXXXX AWR7 [R/W] B, H, W XXXXXXXX XXXXXXXX +2 +3 Block Reserved T-unit 000684H (Continued) 45 MB91301 Series Address 00068CH to 0007F8H 0007FCH 000800H to 000AFCH 000B00H 000B04H 000B08H 000B0CH 000B10H 000B14H to 000B1CH 000B20H 000B24H 000B28H 000B2CH 000B30H 000B34H 000B38H 000B3CH 000B40H 000B44H Register +0 +1 MODR [W] *2 XXXXXXXX ESTS0 [R/W] B X0000000 ECTL0 [R/W] B 0X000000 ECNT0 [W] B XXXXXXXX ESTS1 [R/W] B XXXXXXXX ECTL1 [R/W] B 00000000 ECNT1 [W] B XXXXXXXX ESTS2 [R] B 1XXXXXXX ECTL2 [W] B 000X0000 EUSA [W] B XXX00000 ECTL3 [R/W] B 00X00X11 EDTC [W] B 0000XXXX +2 +3 Block Reserved T-unit Reserved EWPT [R] H 00000000 00000000 EDTR0 [W] H XXXXXXXX XXXXXXXX ECTL4 [R] ([R/W]) B ECTL5 [R] ([R/W]) B - 0X00000 - - - - 000X EDTR1 [W] H XXXXXXXX XXXXXXXX EIA0 [W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIA1 [W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIA2 [W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIA3 [W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIA4 [W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIA5 [W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIA6 [W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIA7 [W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EDTA [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EDTM [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX (Continued) DSU (Evaluation chip only) 46 MB91301 Series Address 000B48H 000B4CH 000B50H 000B54H 000B58H 000B5CH 000B60H 000B64H 000B68H 000B6CH 000B70H to 000FFCH 001000H 001004H 001008H 00100CH 001010H 001014H 001018H 00101CH 001020H Register +0 +1 +2 +3 EOA0 [W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EOA1 [W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EPCR [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EPSR [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIAM0 [W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIAM1 [W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EOAM0/EODM0 [W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EOAM1/EODM1 [W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EOD0 [W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EOD1 [W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMASA0 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMADA0 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMASA1 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMADA1 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMASA2 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMADA2 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMASA3 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMADA3 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMASA4 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Block DSU (Evaluation chip only) Reserved DMAC (Continued) 47 MB91301 Series (Continued) Address 001024H 001028H to 001FFCH Register +0 +1 +2 +3 DMADA4 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Block DMAC Reserved *1 : Byte access is not permitted for the lower 16 bits of DMAC0 to DMAC4 (DTC15 to DTC0) . *2 : This register is accessed through mode vector fetch; it cannot be accessed in normal mode. 48 MB91301 Series INTERRUPT VECTORS Interrupt Reset Mode vector System reserved System reserved System reserved System reserved System reserved Coprocessor absent trap Coprocessor error trap INTE instruction Instruction break exception Operand break trap Step trace trap NMI request (tool) Undefined instruction exception NMI request External interrupt 0 External interrupt 1 External interrupt 2 External interrupt 3 External interrupt 4 External interrupt 5 External interrupt 6 External interrupt 7 Reload timer 0 Reload timer 1 Reload timer 2 UART0 (RX completed) UART1 (RX completed) UART2 (RX completed) UART0 (TX completed) UART1 (TX completed) UART2 (TX completed) Interrupt No. 10 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 16 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 Interrupt level*1 15 (FH) fixed ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 ICR16 Offset 3FCH 3F8H 3F4H 3F0H 3ECH 3E8H 3E4H 3E0H 3DCH 3D8H 3D4H 3D0H 3CCH 3C8H 3C4H 3C0H 3BCH 3B8H 3B4H 3B0H 3ACH 3A8H 3A4H 3A0H 39CH 398H 394H 390H 38CH 388H 384H 380H 37CH TBR default address*2 000FFFFCH 000FFFF8H 000FFFF4H 000FFFF0H 000FFFECH 000FFFE8H 000FFFE4H 000FFFE0H 000FFFDCH 000FFFD8H 000FFFD4H 000FFFD0H 000FFFCCH 000FFFC8H 000FFFC4H 000FFFC0H 000FFFBCH 000FFFB8H 000FFFB4H 000FFFB0H 000FFFACH 000FFFA8H 000FFFA4H 000FFFA0H 000FFF9CH 000FFF98H 000FFF94H 000FFF90H 000FFF8CH 000FFF88H 000FFF84H 000FFF80H 000FFF7CH RN 6 7 11 12 8 9 10 0 1 2 3 4 5 (Continued) 49 MB91301 Series Interrupt DMAC0 (end, error) DMAC1 (end, error) DMAC2 (end, error) DMAC3 (end, error) DMAC4 (end, error) A/D PPG0 PPG1 PPG2 PPG3 System reserved U-TIMER0 U-TIMER1 U-TIMER2 Time base timer overflow I C I/F0 I2C I/F1 System reserved System reserved 16 bit Free Run Timer ICU0 (load) ICU1 (load) ICU2 (load) ICU3 (load) System reserved System reserved System reserved System reserved System reserved System reserved Delay interrupt bit System reserved (Used by REALOS) System reserved (Used by REALOS) System reserved 2 Interrupt No. 10 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 16 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 Interrupt level*1 ICR17 ICR18 ICR19 ICR20 ICR21 ICR22 ICR23 ICR24 ICR25 ICR26 ICR27 ICR28 ICR29 ICR30 ICR31 ICR32 ICR33 ICR34 ICR35 ICR36 ICR37 ICR38 ICR39 ICR40 ICR41 ICR42 ICR43 ICR44 ICR45 ICR46 ICR47 Offset 378H 374H 370H 36CH 368H 364H 360H 35CH 358H 354H 350H 34CH 348H 344H 340H 33CH 338H 334H 330H 32CH 328H 324H 320H 31CH 318H 314H 310H 30CH 308H 304H 300H 2FCH 2F8H 2F4H TBR default address*2 000FFF78H 000FFF74H 000FFF70H 000FFF6CH 000FFF68H 000FFF64H 000FFF60H 000FFF5CH 000FFF58H 000FFF54H 000FFF50H 000FFF4CH 000FFF48H 000FFF44H 000FFF40H 000FFF3FH 000FFF38H 000FFF34H 000FFF30H 000FFF2CH 000FFF28H 000FFF24H 000FFF20H 000FFF1CH 000FFF18H 000FFF14H 000FFF10H 000FFF0CH 000FFF08H 000FFF04H 000FFF00H 000FFEFCH 000FFEF8H 000FFEF4H RN 15 13 14 (Continued) 50 MB91301 Series (Continued) Interrupt System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved Used by INT instruction Interrupt No. 10 67 68 69 70 71 72 73 74 75 76 77 78 79 80 to 255 16 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 to FF Interrupt level*1 Offset 2F0H 2ECH 2E8H 2E4H 2E0H 2DCH 2D8H 2D4H 2D0H 2CCH 2C8H 2C4H 2C0H 2BCH to 000H TBR default address*2 000FFEF0H 000FFEECH 000FFEE8H 000FFEE4H 000FFEE0H 000FFEDCH 000FFED8H 000FFED4H 000FFED0H 000FFECCH 000FFEC8H 000FFEC4H 000FFEC0H 000FFEBCH to 000FFC00H RN *1 : ICRs are registers built in the interrupt controller to set interrupt levels for individual interrupt requests. The ICRs are provided for the different interrupt levels. *2 : The TBR is the register holding the start address of the EIT vector table. The TBR value and the offset value preset for each EIT source are added together to be the vector address. Note: The 1 Kbyte area from the TBR address is the EIT vector area. The vector size is 4 bytes and the relationship between vector number and vector address is expressed as follows: Vctadr = TBR + vctofs = TBR + (3FCH - 4 x vct) vctadr : vector address vctofs : vector offset vct : vector number 51 MB91301 Series INSTRUCTION CACHE The instruction cache is a fast local memory for temporary storage. Once an instruction code is accessed from external slower memory, the instruction cache holds the instruction code inside to increase the speed of accessing the same code from then on. By setting the RAM mode, the instruction cache data RAM is made directly read/write-accessible by software. * Configuration * FR family's basic instruction length : Two bytes * Block layout : Two-way set associative * Blocks : 128 blocks per way 16 bytes per block ( = 4 sub-blocks) 4 bytes per sub-block ( = 1 bus access unit) * Instruction Cache Configuration 4 bytes 4 bytes I3 4 bytes I2 4 bytes I1 4 bytes I0 Way 1 Cash tag 128 block Cash tag Way 2 Cash tag 128 block Sub block 3 Sub block 2 Sub block 1 Sub block 0 block 0 Sub block 3 Sub block 2 Sub block 1 Sub block 0 block 127 Sub block 3 Sub block 2 Sub block 1 Sub block 0 block 0 Cash tag Sub block 3 Sub block 2 Sub block 1 Sub block 0 block 127 52 MB91301 Series * Instruction Cache Tags Way 1 31 09 08 Vacancy Address tag 07 SBV3 06 SBV2 05 SBV1 04 SBV0 09 03 TAGV 08 Vacancy 02 Vacancy 01 LRU 00 ETLK Way 2 31 Address tag 07 SBV3 06 SBV2 05 SBV1 04 SBV0 03 TAGV 02 01 00 ETLK Vacancy [bit 31 to bit 9] Address tag The address tag stores the upper 23 bits of the memory address of the instruction cached in the corresponding block. For example, memory address IA of the instruction data stored in sub-block k in block i is obtained from the following equation: IA = address tag x 29 + i x 24 + k x 22 The address tag is used to check for a match with the instruction address requested for access by the CPU. The CPU and cache behave as follows depending on the result of the tag check: * When the requested instruction data exists in the cache (hit), the cache transfers the data to the CPU within the cycle. * When the requested instruction data does not exist in the cache (miss), the CPU and cache obtain the data loaded by external access at the same time. [bit 7 to bit4] SBV3 to SBV0 : Sub-block validation When SBVn contains "1", the corresponding sub-block holds the current instruction data at the address located by the tag. Each sub-block usually holds two instructions (excluding immediate-value transfer instructions). [bit 3] TAGV : Tag validation bit This bit indicates whether the address tag value is valid. When the bit contains "0", the corresponding block is invalid regardless of the settings of the sub-block validation bits. (The bit is set to "0" when the cache is flushed.) [bit 1] LRU (only in way 1) This bit exists only in the instruction cache tag in way 1. The bit indicates way 1 or 2 as the way containing the last entry accessed in the selected set. When set to "1", the LRU bit indicates that the entry of the set in way 1 is the last entry accessed. When set to "0", it indicates that the one in way 2 is the last entry accessed. [bit 0] ETLK : Entry lock This bit is used to lock all the entries in the block corresponding to the tag in the cache. When the ETLK bit is set to "1", the entries are locked and are not updated when a cache miss occurs. Note, however, that invalid sub-blocks are updated. If a cache miss occurs with both of ways 1 and 2 in the entry lock states, access to external memory takes place after losing one cycle used for evaluating the cache miss. 53 MB91301 Series Control Registers * Cache Size Register (ISIZE) bit Address : 00000307H 7 6 5 4 3 2 1 SIZE1 R/W 0 SIZE0 R/W Initial value - - - - - - 10B * Instruction Cache Control Register (ICHCR) The instruction cache (I-cache) control register (ICHCR) controls the operations of the instruction cache. Writing a value to the ICHCR has no effect on the caching of any instruction fetched within three cycles that follow. bit Address : 000003E7H 7 RAM R/W 6 5 GBLK R/W 4 ALFL R/W 3 EOLK R/W 2 ELKR R/W 1 FLSH R/W 0 ENAB R/W Initial value 0 - 000000B Address 00010000H 00010200H 00010400H 00010600H 00010800H 00010FFFH 00014000H 00014200H 00014400H 00014600H 00014800H 00014FFFH 00018000H 00018200H 00018400H 00018600H 00018800H 00018FFFH 0001C000H 0001C200H 0001C400H 0001C600H 0001C800H 0001CFFFH Cache off RAM off Cache off RAM on TAG1 Cache 4 K RAM off Cache 4 K Cache 2 K RAM on RAM off TAG1 Cache 2 K Cache 1 K RAM on RAM off TAG1 <TAG1> Cache RAM on TAG1 <TAG1> <TAG1> <TAG1> <TAG1> TAG2 <TAG2> <TAG2> <TAG2> <TAG2> $RAM1 <TAG1> TAG2 <TAG1> TAG2 <TAG1> TAG2 <TAG2> <TAG2> IRAM1 IRAM1 <TAG2> $RAM1 IRAM1 <TAG2> $RAM1 IRAM1 <$RAM1> $RAM2 IRAM2 IRAM2 <$RAM2> IRAM2 <IRAM2> IRAM1 <IRAM1> IRAM1 <$RAM1> $RAM2 IRAM2 <$RAM2> <IRAM1> IRAM2 <IRAM1> IRAM2 <$RAM1> $RAM2 <IRAM1> <IRAM2> <IRAM2> <$RAM2> <IRAM2> TAG RAM 00010000H 00010004H 00010008H 0001000CH 00010010H 00010014H TAG1 TAG RAM (way1) $RAM1 Cache RAM (way1) TAG2 TAG RAM (way2) $RAM2 Cache RAM (way2) <> Mirror area RAM on/offRAM bit = I/O Cache RAM Entry at address 00x 00018000H 00018004H Mirror of 00x Entry at address 00x Mirror of 00x 00018008H 0001800CH 00018010H 00018014H IRAM1 I-bus RAM (way1) IRAM1 I-bus RAM (way2) Instruction at address 000 (SBV0) Instruction at address 004 (SBV1) Instruction at address 008 (SBV2) Instruction at address 00C (SBV3) Instruction at address 010 (SBV0) Instruction at address 014 (SBV1) 54 MB91301 Series Address 000H 200H 400H 600H 000H 200H 400H 600H Cache 4 K Cache 2 K $RAM1 Cache 1 K $RAM1 IRAM1 $RAM2 IRAM2 Cache off $RAM1 IRAM1 $RAM2 $RAM2 IRAM2 IRAM1 IRAM2 ROMA = 0 (ROM absent) Address 00000000H Direct area 00010000H 00020000H 00030000H 00040000H 00100000H FFFFFFFFH IRAM ROMA = 1 (ROM present) Direct area IRAM (Even the D-bus RAM area is cashed, when it is transferred to the IA-Bus.) Internal ROM/RAM area should be cached. Each chip-select area can be set as a non-cache area. Cache area Internal memory Cache area 55 MB91301 Series PERIPHERAL RESOURCES 1. External Bus Interface Controller * External Bus Interface Controller Features * Maximum output address width = 32-bit (4 Gbytes memory space) * Various different types of external memory (8-bit, 16-bit, or 32-bit devices) can be directly connected and the controller can support multiple devices with different access timings. Asynchronous SRAM, asynchronous ROM/FLASH memory (supports multiple write strobe access or byteenable access) Page mode ROM/FLASH memory (2, 4, or 8 page size) Burst mode ROM/FLASH memory Address/data multiplexed bus (8-bit or 16-bit width only) Synchronous memory (built-in ASIC memory, etc.) Note: Synchronous SRAM cannot be directly connected. * Memory can be divided into eight independent banks (chip select areas) with a separate chip select output for each bank. The size of each area can be set in 64 Kbytes increments (the size of each chip select area can range from 64 Kbytes to 2 Gbytes) Each area can be located anywhere in the physical address space (subject to boundary limitations based on the area size) * The following functions can be set independently for each chip select area : Chip select area enable/disable (Access is not performed to disabled areas) Setting of an access timing type to support each type of memory (For SDRAM, only the CS6 and CS7 areas can be connected.) Detailed access timing settings (wait cycles and similar settings for each access type) Data bus width (8-bit, 16-bit, 32-bit) Byte-ordering setting (big or little endian) Note: The CS0 area must be big endian. Write-prohibit setting (read-only areas) Enable or disable loading into built-in cache Enable or disable prefetch function Maximum burst length setting (1, 2, 4, 8) * Different detailed timing settings can be set for each timing type Even for the same type, different settings can be used for each chip select area. Up to 15 auto-wait cycles can be specified. (For asynchronous SRAM, ROM, Flash, and I/O areas) The bus cycle can be extended by the external RDY input. (For asynchronous SRAM, ROM, Flash, and I/O areas) Fast access wait and page wait settings are supported (For burst/page mode ROM and Flash areas) Idle cycles, recovery cycles, setup delays, and similar can be inserted. Capable of setting timing values such as the CAS latency and RAS-CAS delay (SDRAM area) Capable of controlling the distributed/centralized auto-refresh, self-refresh, and other refresh timings (SDRAM area) * DMA supports fly-by transfer Transfer between memory and I/O can be performed by a single access. Memory wait cycles can be synchronized with the I/O wait period during fly-by transfer. Hold times can be maintained by extending access to the data source only. Separate idle and recovery cycle settings can be specified for use in fly-by transfer. * Supports external bus arbitration using BRQ and BGRNT. * Pins not used by the external interface can be set as general purpose I/O ports. 56 MB91301 Series * Block Diagram Internal address bus Internal data bus 32 32 External data bus write buffer switch MUX read buffer switch DATA BLOCK ADDRESS BLOCK +1 or +2 External address bus address buffer ASR ASZ comparator CS0 to CS7 SDRAM control SRAS, SCAS, SWE, MCLKE, DQMUU, DQMUL, DQMLU, DQMLL under flow RCR refresh counter External pin controller All block control registers & control RD WR0, WR1, WR2, WR3, AS, BAA BRQ BGRNT RDY 57 MB91301 Series * I/O pin External interface pin (Some pins are general purpose pins.) The following shows I/O pins of each interface. * Normal bus interface A23 to A00, D31 to D00 (AD15 to AD00) CS0, CS1, CS2, CS3, CS4, CS5, CS6, CS7 AS, SYSCLK, MCLK, RD WR, WR0 (UUB) , WR1 (ULB) , WR2 (ULB) , WR3 (LLB) , RDY, BRQ, BGRNT * Memory interface MCLK, MCLKE MCLKI (for SDRAM) LBA ( = AS) , BAA (for burst ROM/FLASH) SRAS, SCAS, SWE ( = WR) (for SDRAM) DQMUU, DQMUL, DQMLU, DQMLL (for SDRAM ( = WR0, WR1, WR2, WR3) ) * DMA interface IOWR, IORD DACK0, DACK1 DREQ0, DREQ1 DEOP0, DEOP1 58 MB91301 Series * Register List 31 24 23 ASR0 ASR1 ASR2 ASR3 ASR4 ASR5 ASR6 ASR7 AWR0 AWR2 AWR4 AWR6 MCRA Reserved IOWR0 Reserved CSER RCR Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved (MODR) MCRB Reserved IOWR1 Reserved CHER 16 15 08 07 ACR0 ACR1 ACR2 ACR3 ACR4 ACR5 ACR6 ACR7 AWR1 AWR3 AWR5 AWR7 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved TCR Reserved Reserved Reserved Reserved Reserved Reserved 00 Area select registers 0 to 7 (ASR0 to ASR7) Area configuration registers 0 to 7 (ACR0 to ACR7) Area weight register (AWR0 to AWR7) Memory setting register (For SDRAM/FCRAM auto-precharge OFF mode) (MCRA) Memory setting register (For FCRAM auto-precharge ON mode) (MCRB) DMAC I/O wait registers (IOWR0 and IOWR1) Chip-select area enable register (CSER) Cache fetch enable register (CHER) Terminal and timing control register (TCR) Refresh control register (RCR) Notes : * Reserved indicates a reserved register. When writing, always set to "0". * The MODR register cannot be accessed by the user program. 59 MB91301 Series 2. I/O Ports MB91301 series pins can be used as I/O ports when not set for use by the external bus interface or the various peripheral I/O functions. * I/O port (with pull-up resistor) block diagram Port Bus PDR read Peripheral input 0 1 Pull-up resistor (approx. 25 k) Pin Peripheral output PDR 1 0 PFR DDR PCR PCR = 0 : No pull-up resistor PCR = 1 : Use pull-up resistor PDR : Port Data Register DDR : Data Direction Register PFR : Port Function Register PCR : Pull-up Control Register Note : For port output, the pull-up resistor is disabled irrespective of the setting. I/O ports with pull-up resistors have the following registers : * PDR (Port Data Register) * DDR (Data Direction Register) * PFR (Port Function Register) * PCR (Pull-up Control Register) I/O ports have three following modes * When port is in input mode (PFR = "0" & DDR = "0") PDR read : Reads the level of the corresponding external pin. PDR write : Writes the value to the PDR. * When port is in output mode (PFR = "0" & DDR = "1") PDR read : Reads the PDR value. PDR write : Outputs the PDR value to the corresponding external pin. * When port is in peripheral output mode (PFR = "1" & DDR = "X") PDR : Reads the value of the corresponding peripheral output. PDR write : Writes the value to the PDR. 60 MB91301 Series Notes : * Use byte access to access ports. * The external bus function has priority for port 0 to port A when these are used as external bus pins. Accordingly, writing to the DDR has no effect on the pin input/output setting while the pins are operating as external bus pins. The value set in the DDR becomes meaningful when the PFR register is modified to set the pins as general purpose ports. * In stop mode (HIZ = 0), the pull-up resistor control register setting is used. * In stop mode (HIZ = 1), the pull-up resistor control register (PCR) setting is ignored during hardware standby. * Using pull-up resistors is prohibited when these pins are used as external bus pins. In this case, do not write "1" to the corresponding bit in the pull-up resistor control register (PCR). 61 MB91301 Series * Port Data Register (PDR) PDR0 Address : 00000000H PDR1 Address : 00000001H PDR2 Address : 00000002H PDR6 Address : 00000006H PDR8 Address : 00000008H PDR9 Address : 00000009H PDRA Address : 0000000AH PDRB Address : 0000000BH PDRG Address : 00000010H PDRH Address : 00000011H PDRJ Address : 00000013H 7 P07 R/W 7 P17 R/W 7 P27 R/W 7 P67 R/W 7 P87 R/W 7 R/W 7 PA7 R/W 7 PB7 R/W 7 PG7 R/W 7 R/W 7 PJ7 R/W 6 P06 R/W 6 P16 R/W 6 P26 R/W 6 P66 R/W 6 P86 R/W 6 P96 R/W 6 PA6 R/W 6 PB6 R/W 6 PG6 R/W 6 R/W 6 PJ6 R/W 5 P05 R/W 5 P15 R/W 5 P25 R/W 5 P65 R/W 5 P85 R/W 5 P95 R/W 5 PA5 R/W 5 PB5 R/W 5 PG5 R/W 5 R/W 5 PJ5 R/W 4 P04 R/W 4 P14 R/W 4 P24 R/W 4 P64 R/W 4 P84 R/W 4 P94 R/W 4 PA4 R/W 4 PB4 R/W 4 PG4 R/W 4 R/W 4 PJ4 R/W 3 P03 R/W 3 P13 R/W 3 P23 R/W 3 P63 R/W 3 P83 R/W 3 P93 R/W 3 PA3 R/W 3 PB3 R/W 3 PG3 R/W 3 R/W 3 PJ3 R/W 2 P02 R/W 2 P12 R/W 2 P22 R/W 2 P62 R/W 2 P82 R/W 2 P92 R/W 2 PA2 R/W 2 PB2 R/W 2 PG2 R/W 2 PH2 R/W 2 PJ2 R/W 1 P01 R/W 1 P11 R/W 1 P21 R/W 1 P61 R/W 1 P81 R/W 1 P91 R/W 1 PA1 R/W 1 PB1 R/W 1 PG1 R/W 1 PH1 R/W 1 PJ1 R/W 0 P00 R/W 0 P10 R/W 0 P20 R/W 0 P60 R/W 0 P80 R/W 0 P90 R/W 0 PA0 R/W 0 PB0 R/W 0 PG0 R/W 0 PH0 R/W 0 PJ0 R/W Initial value XXXXXXXXB Initial value XXXXXXXXB Initial value XXXXXXXXB Initial value XXXXXXXXB Initial value XXXXXXXXB Initial value - XXXXXXXB Initial value XXXXXXXXB Initial value XXXXXXXXB Initial value XXXXXXXXB Initial value - - - - - XXXB Initial value XXXXXXXXB * PDR0 to PDR2, PDR6, PDR8 to PDRB, PDRG, PDRH and PDRJ are the I/O data registers for the I/O pots. * The corresponding PDR0 to DDRJ and PFR6 to PFRJ registers control input/output. * P00 to P07, P10 to P17 and P20 to P27 do not have a PFR (port function register). 62 MB91301 Series * Data Direction Register (DDR) DDR0 Address : 00000600H DDR1 Address : 00000601H DDR2 Address : 00000602H DDR6 Address : 00000606H DDR8 Address : 00000608H DDR9 Address : 00000609H DDRA Address : 0000060AH DDRB Address : 0000060BH DDRG Address : 00000400H DDRH Address : 00000401H DDRJ Address : 00000403H 7 P07 R/W 7 P17 R/W 7 P27 R/W 7 P67 R/W 7 P87 R/W 7 R/W 7 PA7 R/W 7 PB7 R/W 7 PG7 R/W 7 R/W 7 PJ7 R/W 6 P06 R/W 6 P16 R/W 6 P26 R/W 6 P66 R/W 6 P86 R/W 6 P96 R/W 6 PA6 R/W 6 PB6 R/W 6 PG6 R/W 6 R/W 6 PJ6 R/W 5 P05 R/W 5 P15 R/W 5 P25 R/W 5 P65 R/W 5 P85 R/W 5 P95 R/W 5 PA5 R/W 5 PB5 R/W 5 PG5 R/W 5 R/W 5 PJ5 R/W 4 P04 R/W 4 P14 R/W 4 P24 R/W 4 P64 R/W 4 P84 R/W 4 P94 R/W 4 PA4 R/W 4 PB4 R/W 4 PG4 R/W 4 R/W 4 PJ4 R/W 3 P03 R/W 3 P13 R/W 3 P23 R/W 3 P63 R/W 3 P83 R/W 3 P93 R/W 3 PA3 R/W 3 PB3 R/W 3 PG3 R/W 3 R/W 3 PJ3 R/W 2 P02 R/W 2 P12 R/W 2 P22 R/W 2 P62 R/W 2 P82 R/W 2 P92 R/W 2 PA2 R/W 2 PB2 R/W 2 PG2 R/W 2 PH2 R/W 2 PJ2 R/W 1 P01 R/W 1 P11 R/W 1 P21 R/W 1 P61 R/W 1 P81 R/W 1 P91 R/W 1 PA1 R/W 1 PB1 R/W 1 PG1 R/W 1 PH1 R/W 1 PJ1 R/W 0 P00 R/W 0 P10 R/W 0 P20 R/W 0 P60 R/W 0 P80 R/W 0 P90 R/W 0 PA0 R/W 0 PB0 R/W 0 PG0 R/W 0 PH0 R/W 0 PJ0 R/W Initial value 00000000B Initial value 00000000B Initial value 00000000B Initial value 00000000B Initial value 00000000B Initial value - 0000000B Initial value 00000000B Initial value 00000000B Initial value 00000000B Initial value - - - - - 000B Initial value 00000000B DDR0 to DDR2, DDR6, DDR8 to DDRB, DDRG, DDRH and DDRJ control the direction (input or output) of each bit in the corresponding port. When PFR = 0 DDR = 0 : Port input DDR = 1 : Port output When PFR = 1 DDR = 0 : Peripheral input DDR = 1 : Peripheral output 63 MB91301 Series * Pull-up Resistor Control Register (PCR) PCR0 bit 00000620H 7 P07 R/W 6 P06 R/W 6 P16 R/W 6 P26 R/W 6 P66 R/W 6 P86 R/W 6 P96 R/W 6 PA6 R/W 6 PB6 R/W 6 R/W 5 P05 R/W 5 P15 R/W 5 P25 R/W 5 P65 R/W 5 P85 R/W 5 P95 R/W 5 PA5 R/W 5 PB5 R/W 5 R/W 4 P04 R/W 4 P14 R/W 4 P24 R/W 4 P64 R/W 4 P84 R/W 4 P94 R/W 4 PA4 R/W 4 PB4 R/W 4 R/W 3 P03 R/W 3 P13 R/W 3 P23 R/W 3 P63 R/W 3 P83 R/W 3 R/W 3 PA3 R/W 3 PB3 R/W 3 R/W 2 P02 R/W 2 P12 R/W 2 P22 R/W 2 P62 R/W 2 P82 R/W 2 R/W 2 PA2 R/W 2 PB2 R/W 2 PH2 R/W 1 P01 R/W 1 P11 R/W 1 P21 R/W 1 P61 R/W 1 P81 R/W 1 P91 R/W 1 PA1 R/W 1 PB1 R/W 1 PH1 R/W 0 P00 R/W 0 P10 R/W 0 P20 R/W 0 P60 R/W 0 P80 R/W 0 R/W 0 PA0 R/W 0 PB0 R/W 0 PH0 R/W Address : Initial value 00000000B Address : PCR1 bit 00000621H 7 P17 R/W Initial value 00000000B Address : PCR2 bit 00000622H 7 P27 R/W Initial value 00000000B Address : PCR6 bit 00000626H 7 P67 R/W Initial value 00000000B Address : PCR8 bit 00000628H 7 P87 R/W Initial value 00000000B Address : PCR9 bit 00000629H 7 R/W Initial value - 000 - - 0 -B Address : PCRA bit 0000062AH 7 PA7 R/W Initial value 00000000B Address : PCRB bit 0000062BH 7 PB7 R/W Initial value 00000000B Address : PCRH bit 00000421H 7 R/W Initial value - - - - - 000B PCR0 to PCR2, PCR6, PCR8 to PCRB, PCRG, PCRH and PCRJ control the pull-up resistors for the corresponding port. PCR = 0 : No pull-up resistor PCR = 1 : Use pull-up resistor 64 MB91301 Series * Port Function Register (PFR) Address : PFR6 bit 00000616H 7 A23E R/W 6 A22E R/W 5 A21E R/W 4 A20E R/W 4 R/W 4 ASXE R/W 3 A19E R/W 3 R/W 3 R/W 2 A18E R/W 2 BRQE R/W 2 1 A17E R/W 1 R/W 1 0 A16E R/W 0 R/W 0 SYSE R/W Initial value 11111111B Address : PFR8 bit 7 6 5 00000618H WR3XE WR2XE WR1XE R/W R/W 6 WRXE R/W R/W 5 BAAE R/W Initial value 111 - - 0 - -B Address : PFR9 bit 00000619H 7 R/W MCKE MCKEE R/W R/W Initial value - 0000111B Address : PFRA1 bit 7 6 5 4 3 2 1 0 0000061AH CS7XE CS6XE CS5XE CS4XE CS3XE CS2XE CS1XE CS0XE R/W R/W 6 AK12 R/W 6 DWRE R/W 6 R/W 6 SOE2 R/W 6 R/W 6 PPE0 R/W 6 R/W R/W 5 AK11 R/W 5 PPE1 R/W 5 PPE2 R/W 5 R/W 5 R/W 5 SCE1 R/W 5 R/W R/W 4 AK10 R/W 4 R/W 4 R/W 4 R/W 4 R/W 4 SOE1 R/W 4 R/W R/W 3 DES0 R/W 3 R/W 3 R/W 3 R/W 3 R/W 3 R/W 3 TEST1 R/W R/W 2 AK02 R/W 2 R/W 2 R/W 2 R/W 2 R/W 2 SCE0 R/W 2 TEST0 R/W R/W 1 AK01 R/W 1 AKH1 R/W 1 R/W 1 R/W 1 PPE3 R/W 1 SOE0 R/W 1 I2CE1 R/W R/W 0 AK00 R/W 0 AKH0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 I2CE0 R/W Initial value 11111111B Address : PFRB1 bit 0000061BH 7 DES1 R/W Initial value 00000000B Address : PFRB2 bit 0000061CH 7 DRDE R/W Initial value 000 - - - 00B Address : PFRA2 bit 0000061EH 7 R/W Initial value - - 0 - - - - -B Address : PFRG bit 00000410H 7 SCE2 R/W Initial value 00 - - - - - -B Address : PFRH bit 00000411H 7 R/W Initial value - - - - - - 0 -B Address : PFRJ bit 00000413H 7 R/W Initial value - 000 - 00 -B Address : PFR61 bit 00000617H 7 R/W Initial value - - - - 0000 B PFR6, PFR8 to PFRB, PFRA2, PFRG, PFRH and PFRJ control the output for the corresponding external bus interface or peripheral output bit. Always write "0" to unused bits in the PFR. 65 MB91301 Series 3. Interrupt Controller The interrupt controller receives and processes interrupts. * Hardware Configuration The interrupt controller consists of the following : * ICR register * Interrupt priority determination circuit * Interrupt level and interrupt number (vector) generator * Hold request removal request generator * Principal Functions The main functions of the interrupt controller are as follows : * Detect NMI and interrupt requests * Prioritize interrupts (according to level and number) * Notify interrupt level of selected interrupt request (to CPU) * Notify interrupt number of selected interrupt request (to CPU) If an NMI or interrupt request with an interrupt level other than "11111B" occurs, notify recovery from stop mode (to CPU) * Generate hold request removal requests to the bus master * Block Diagram ("1" when LEVEL 11111B) ("1" when LEVEL 11111B) UNMI WAKEUP Determine order priority Determine order ofof priority NMI NMI processing processing 5 LEVEL4 to LEVEL40 LEVEL LEVEL determination determination RI00 ICR00 VECTOR VECTOR 6 determination determination LEVEL, LEVEL, VECTOR VECTOR generageneration tion HLDREQ HLDREQ removal removal request request MHALTI VCT5 to VCT50 ICR47 RI47 (DLYIRQ) R-bus 66 MB91301 Series * Register List bit 7 6 5 4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 Address : 00000440H Address : 00000441H Address : 00000442H Address : 00000443H Address : 00000444H Address : 00000445H Address : 00000446H Address : 00000447H Address : 00000448H Address : 00000449H Address : 0000044AH Address : 0000044BH Address : 0000044CH Address : 0000044DH Address : 0000044EH Address : 0000044FH Address : 00000450H Address : 00000451H Address : 00000452H Address : 00000453H Address : 00000454H Address : 00000455H Address : 00000456H Address : 00000457H Address : 00000458H Address : 00000459H Address : 0000045AH Address : 0000045BH Address : 0000045CH Address : 0000045DH Address : 0000045EH Address : 0000045FH ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 ICR16 ICR17 ICR18 ICR19 ICR20 ICR21 ICR22 ICR23 ICR24 ICR25 ICR26 ICR27 ICR28 ICR29 ICR30 ICR31 (Continued) 67 MB91301 Series (Continued) bit 7 6 5 4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 Address : 00000460H Address : 00000461H Address : 00000462H Address : 00000463H Address : 00000464H Address : 00000465H Address : 00000466H Address : 00000467H Address : 00000468H Address : 00000469H Address : 0000046AH Address : 0000046BH Address : 0000046CH Address : 0000046DH Address : 0000046EH Address : 0000046FH ICR32 ICR33 ICR34 ICR35 ICR36 ICR37 ICR38 ICR39 ICR40 ICR41 ICR42 ICR43 ICR44 ICR45 ICR46 ICR47 Address : 0000045H MHALTI LVL4 LVL3 LVL2 LVL1 LVL0 HRCL 68 MB91301 Series 4. External Interrupt/NMI Control Block The external interrupt control block controls external interrupt requests input to the NMI and INT0 to INT7 pins. The interrupt trigger level can be selected from "H", "L", "rising edge", or "falling edge" (except for NMI). * Block Diagram R-bus 8 Interrupt enable register 9 INT0 to INT7 NMI Interrupt request 9 Gate Request F/F Edge detection circuit 8 Interrupt request register 8 Interrupt level setting register * Register List External interrupt enable register (ENIR) bit 7 6 5 EN7 EN6 EN5 4 EN4 3 EN3 2 EN2 1 EN1 0 EN0 External interrupt request register (EIRR) bit 15 14 13 ER7 ER6 ER5 12 ER4 11 ER3 10 ER2 9 ER1 8 ER0 Request level setting register (ELVR) bit 15 14 LB7 LA7 6 LA3 13 LB6 5 LB2 12 LA6 4 LA2 11 LB5 3 LB1 10 LA5 2 LA1 9 LB4 1 LB0 8 LA4 0 LA0 bit 7 LB3 69 MB91301 Series 5. Delay Interrupt Module The delay interrupt module is used to generate interrupts for task switching. This module can be used to generate and cancel interrupts to the CPU via software. * Block Diagram R-bus DLYI Interrupt request * Register List Delay interrupt control register (DICR) bit 7 6 5 4 3 2 1 0 DLYI 70 MB91301 Series 6. PPG Timer The PPG timer can output highly precise PWM waveforms efficiently. The MB91301 series contains four channels of PPG timer. * Features of the PPG Timer * Each channel consists of a 16-bit down counter, a 16-bit data register with cycle setting buffer, a 16-bit compare register with duty setting buffer, and pin control section. * The count clocks for the 16-bit down counter can be selected from the following four types : Internal clock , /4, /16, /64 * The counter is initialized to "FFFFH" at a reset or counter borrow. * Each channel has a PPG output. * Register outline Cycle setting register: Reload data register with buffer Duty setting register: Compare register with buffer Transfer from the buffer takes place upon a counter borrow. * Pin control overview A duty match sets the pin control section to 1. (Preferential) A counter borrow resets it to 0. The output value fix mode is available, which can each output all "L" (or "H"). A polarity can also be specified. * An interrupt request can be generated at a combination of the following events : Activation of the PPG timer Counter borrow (cycle match) Duty match Counter borrow (cycle match) or duty match DMA transfer can be initiated by the above interrupt request. * It is possible to set the simultaneous activation of two or more channels by means of software or another interval timer. Restarting during operation can also be set. * The request level to be detected can be selected from among "rising edge", "falling edge", and "both edges". 71 MB91301 Series * Block diagram 16-bit reload timer ch0 16-bit reload timer ch1 TRG input PPG timer ch0 PPG0 General control register 2 4 General control register 1 (resource select) TRG input PPG timer ch1 PPG1 TRG input PPG timer ch2 TRG input PPG timer ch3 PPG2 4 External TRG0 to TRG3 PPG3 * Block diagram for 1 channel PCSR PDUT Prescaler 1/1 1/4 1 / 16 1 / 64 CK cmp Load 16-bit down counter Start Borrow PPG mask S Q PPG output Peripheral clock R Conversion bit Enable TRG input Edge detection Soft trigger Interrupt selection IRQ 72 MB91301 Series * Register List bit 15 7 GCN10 0 General control register 10 GCN20 General control register 20 PTMR0 PCSR0 PDUT0 PCNH0 PCNL0 ch0 timer register ch0 cycle setting register ch0 duty setting register ch0 control status register PTMR1 PCSR1 PDUT1 PCNH1 PCNL1 ch1 timer register ch1 cycle setting register ch1 duty setting register ch1 control status register PTMR2 PCSR2 PDUT2 PCNH2 PCNL2 ch2 timer register ch2 cycle setting register ch2 duty setting register ch2 control status register PTMR3 PCSR3 PDUT3 PCNH3 PCNL3 ch3 timer register ch3 cycle setting register ch3 duty setting register ch3 control status register 73 MB91301 Series 7. 16-Bit Reload Timer The 16-bit timer consists of a 16-bit down-counter, 16-bit reload register, prescaler for generating the internal count clock, and a control register. The clock source can be selected from three internal clock signals (machine clock divided by 2, 8, or 32) or the external event. The interrupt can be used to initiate DMA transfer. The MB91301 series has three 16-bit reload timer channels. * Block Diagram 16 16-bit reload register (TMRLR) 7 Reload 16 16-bit down counter (TMR) UF RELD Count enable OUT CTL. INTE UF CNTE IRQ Re-trigger R-bus Clock selector CSL1 TRG CSL0 3 EXCK IN CTL. 21 23 25 Prescaler clear 3 MOD0 MOD1 External trigger selection External trigger input (TI) CLKP input 3 MOD2 74 MB91301 Series * Register List Control status register (TMCSR) bit 15 14 6 13 5 OUTL 12 4 RELD 11 CSL1 3 INTE 10 CSL0 2 UF 9 MOD2 1 CNTE 8 MOD1 0 TRG bit 7 MOD0 16-bit timer register (TMR) bit 15 0 16-bit reload register (TMRLR) bit 15 0 75 MB91301 Series 8. U-TIMER (16 bit timer for UART baud rate generation) The U-TIMER is a 16-bit timer used to generate the baud rate for the UART. Any desired baud rate can be set using the combination of the chip operating frequency and U-TIMER reload value. The U-TIMER can also be used as an interval timer by generating an interrupt from a count underflow event. The MB91301 series has three U-TIMER channels. When used as an interval timer, two U-TIMER channels can be connected in cascade for a maximum count interval of up to 232 x . Cascade connection is only available for ch0 and ch1 or ch0 and ch2. * Block Diagram 15 UTIMR (reload register) load 15 UTIM (timer) 0 0 clock underflow control (CLKP) (Peripheral clock) MUX ch0 only f.f. to UART under flow U-TIMER 1 76 MB91301 Series * Register List 15 87 UTIM UTIMR UTIMC 0 * U-TIMER (UTIM) Address bit 000064H (ch 0) 00006CH (ch 1) 000074H (ch 2) 15 b15 R 14 b14 R 2 b2 R 1 b1 R 0 b0 R Initial value 00000000 00000000B UTIM contains the timer value. Use a 16-bit transfer instruction to access the register. Reload register (UTIMR) Address bit 15 000064H (ch 0) b15 00006CH (ch 1) W 000074H (ch 2) 14 b14 W 2 b2 W 1 b1 W 0 b0 W Initial value 00000000 00000000B UTIMR is the register that contains the value to be reloaded to UTIM when UTIM causes an underflow. Use a 16-bit transfer instruction to access the register. 77 MB91301 Series 9. UART The UART is a serial I/O port for asynchronous (start-stop synchronized) or CLK synchronized transmission. The MB91301 series has three UART channels. * UART Features * Full duplex double buffer * Asynchronous (start-stop synchronized) or CLK synchronized transmission * Supports multi-processor mode * Fully programmable baud rate The internal timer can be set to any desired baud rate (see "8. U-TIMER" description) * Variable baud rate can be input from an external clock. * Error detection functions (parity, framing, overrun) * Transmission signal format is NRZ * The interrupt can be used to initiate DMA transfer. * The DMAC interrupt can be cleared by writing to the DRCL register. 78 MB91301 Series * Block Diagram Control signal RX interrupt (to CPU) SCK (clock) From U-TIMER Clock selection circuit TX clock RX clock TX interrupt (to CPU) External clock SCK RX control circuit SI (Receive data) Start bit detect circuit Receive bit counter Receive parity counter TX control circuit TX start circuit Send bit counter Send parity counter SO (Send data) Receive status decision circuit RX shifter RX complete SIDR TX shifter TX start SODR Receive error signal for DMA (to DMAC) R - bus MD1 MD0 SMR register CS0 SCKE SCR register PEN P SBL CL A/D REC RXE TXE SSR register PE ORE FRE RDRF TDRE BDS RIE TIE Control signal 79 MB91301 Series * Register List 15 SCR SSR 87 SMR SIDR (R)/SODR (W) 0 (R/W) (R/W) DRCL 8 bit 8 bit (W) Serial input data register Serial output data register (SIDR/SODR) bit 7 D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0 Serial status register (SSR) 7 bit PE 6 ORE 5 FRE 4 RDRF 3 TDRE 2 BDS 1 RIE 0 TIE Serial mode register (SMR) bit 7 MD1 6 MD0 5 4 3 CS0 2 1 SCKE 0 Serial control register (SCR) 7 bit PEN 6 P 5 SBL 4 CL 3 A/D 2 REC 1 RXE 0 TXE DRCL register (DRCL) bit 7 6 5 4 3 2 1 0 80 MB91301 Series 10. A/D Converter (Successive Approximation Type) The A/D converter converts analog input voltages to digital values. * A/D Converter Features * Peripheral clock (CLKP) 140 clock cycle * Minimum conversion time 4.1 s/ch (for machine clock 34 MHz = CLKP) * Built-in sample & hold circuit * Resolution = 10-bit * 4 channel program-selectable analog inputs Single conversion mode : Convert 1 specified channel Scan conversion mode : Continuous conversion of multiple channels. Conversion can be specified for up to 4 channels. * Single, continuous, and stop conversion operation is supported. Single conversion mode : Convert specified channel then stop. Continuous conversion mode : Perform continuous conversion for the selected channel. Stop conversion mode : Perform conversion for one channel, then wait for the next activation trigger (synchronizes the conversion start timing) * DMA transfer can be initiated by an interrupt. * Selectable conversion activation trigger: Software, external trigger (falling edge), or reload timer (rising edge) 81 MB91301 Series * Block Diagram AVCC AVRH AVSS AVR Internal voltage generator Sample & hold circuit AN0 AN1 AN2 AN3 Input switch Successive approximation register Data register (ADCR : 10 bit) Upper 8 bit COPY Data register (ADCR0 to ADCR7 : 8bit) Channel decoder Timing generation circuit Machine clock (CLKP) ATG (External pin trigger) Reload timer ch2 (internal connection) * Register List Control status register (ADCS) bit 15 BUSY 14 INT 6 MD0 13 INTE 5 ANS2 12 CRF 4 ANS1 11 STS1 3 ANS0 10 STS0 2 ANE2 A/D control register (ADCS) Prescaler 9 STRT 1 ANE1 8 0 ANE0 bit 7 MD1 Data register (ADCR) bit 15 14 6 6 13 5 5 12 4 4 11 3 3 10 2 2 9 9 1 1 8 8 0 0 bit 7 7 Conversion result register (ADCR0 to ADCR3) bit 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0 82 R-bus MB91301 Series 11. DMAC (DMA Controller) The DMA controller is used to perform DMA (direct memory access) transfer on the FR family device. Using DMA transfer under the control of the DMA controller improves system performance by enabling data to be transferred at high speed independently of the CPU. * Hardware Configuration * Independent DMA channels x 5 channels * 5-channel independent access control circuits * 32-bit address register (Supports reloading : 2 per channel) * 16-bit transfer count register (Supports reloading : 1 per channel) * 4-bit block count register (1 per channel) * External transfer request input pins : DREQ0, DREQ1 (ch0, ch1 only) * External transfer request acknowledge output pins : DACK0, DACK1 (ch0, ch1 only) * DMA completion output pins : DEOP0, DEOP1 (ch0, ch1 only) * fly-by transfer (memory to I/O , I/O to memory) (ch0, ch1 only) * Two-cycle transfer * Main Functions of the DMA Controller * Supports independent data transfer for multiple channels (5 channels) (1) Priority order (ch 0 > ch 1 > ch 2 > ch 3 > ch 4) (2) Order can be reversed for ch 0 and ch 1 (3) DMAC activation triggers * Input from dedicated external pin (edge detection/level detection, ch 0, ch 1 only) * Request from built-in peripheral (shared interrupt request, including external interrupts) * Software request (register write) (4) Transfer modes * Demand transfer, burst transfer, step transfer, or block transfer Addressing mode: Full 32-bit address (increment/decrement/fixed) (address increment can be in the range-255 to +255) * Data type : byte/half-word/word * Single-shot or reload operation selectable 83 MB91301 Series * Block Diagram Counter Write back DMA transfer request to bus controller Buffer Selector DTC two-stage register DTCR DMA start trigger selection circuit & request acknowledge control Peripheral start request/ Stop input External pin start request/Stop input Counter Buffer Read Write DSS [3:0] Priority circuit To interrupt controller Read/write control Selector Selector BLK register IRQ [4:0] MCLREQ ERIR, EDIR Bus control block Counter buffer DMA control Selector DSAD two-stage register SDAM, SASZ [7:0] SADR Access address Address counter Write back Selector Counter buffer DDAD two-stage register DADM, DASZ [7:0] DADR Write back 5-channel DMAC block diagram 84 Bus control block DDNO DDNO register To bus controller X-bus Status transition circuit Clear peripheral interrupt TYPE, MOD, WS MB91301 Series * Register List bit 31 24 23 16 15 08 07 00 ch 0 control status ch 0 control status ch 1 control status ch 1 control status ch 2 control status ch 2 control status ch 3 control status ch 3 control status ch 4 control status ch 4 control status Overall control register ch 0 transfer source address register register A DMACA0 0000200H register B DMACB0 0000204H register A DMACA1 0000208H register B DMACB1 000020CH register A DMACA2 0000210H register B DMACB2 0000214H register A DMACA3 0000218H register B DMACB3 000021CH register A DMACA4 0000220H register B DMACB4 0000224H bit 31 24 23 16 15 08 07 00 D M A C R 0000240H DMASA0 0001000H DMADA0 0001004H DMASA1 0001008H DMADA1 000100CH DMASA2 0001010H DMADA2 0001014H DMASA3 0001018H DMADA3 000101CH DMASA4 0001020H DMADA4 0001024H ch 0 transfer destination address register ch 1 transfer source address register ch 1 transfer destination address register ch 2 transfer source address register ch 2 transfer destination address register ch 3 transfer source address register ch 3 transfer destination address register ch 4 transfer source address register ch 4 transfer destination address register 85 MB91301 Series 12. I2C Interface I2C interface is the serial I/O port that support INTER IC BUS and functions as the master/slave device on the I2C bus. It has the features below. * Master/slave transmission and reception * Arbitration function * Clock synchronization * Slave address/general call address detection function * Forwarding direction detection function * The function of generating/detecting repeat "START" conditions. * Bus error detection function * 10-bit/7-bit slave address * Control slave address receiving at the master mode * For support multiple slave address * Can be interrupt at transmitting or bus mirror * For normal mode (Max 100 Kbps) /fast mode (Max 400 Kbps) 86 MB91301 Series * Block Diagram (1 ch) ICCR EN IDBL DBL ICCR CS4 CS3 CS2 CS1 CS0 IBSR BB RSC LRB TRX ADT AL R-bus IBCR BER BEIE Interrupt request I2C operating enable Clock enable Clock dividing 2 2345 32 Sync CLKP Shift clock generation Clock select 2 (1/12) Bus busy Repeat start Last Bit Transmission/ reception Shift clock edge change timing Start/stop condition detection Error First Byte Arbitration lost detection SCL0/1 IRQ SDA0/1 INTE INT IBCR SCC MSS ACK GCAA Start Master ACK enable GC-ACK enable End Start/stop condition generation IDAR IBSR AAS GCA ISMK FNSB ITMK ENTB RAL ITBA ITMK ISBA ISMK Slave Global call Slave address comparison 87 MB91301 Series * Register List * Bus control register (IBCR0/1) Address : 000094H/0000B4H 15 BER R/W 14 BEIE R/W 0 13 SCC W 0 12 MSS R/W 0 11 ACK R/W 0 10 GCAA R/W 0 9 INTE R/W 0 8 INT R/W 0 Initial value = > 0 * Bus status register (IBSR0/1) Address : 000095H/0000B5H 7 BB R 6 RSC R 5 AL R 0 4 LRB R 0 3 TRX R 0 2 AAS R 0 1 GCA R 0 0 ADT R 0 Initial value = > 0 0 * 10-bit slave address register (ITBA0/1) Address : 000096H/0000B6H Initial value = > Address : 000097H/0000B7H Initial value = > 15 R 0 7 TA7 R/W 0 14 R 0 6 TA6 R/W 0 13 R 0 5 TA5 R/W 0 12 R 0 4 TA4 R/W 0 11 R 0 3 TA3 R/W 0 10 R 0 2 TA2 R/W 0 9 TA9 R/W 0 1 TA1 R/W 0 8 TA8 R/W 0 0 TA0 R/W 0 (Continued) 88 MB91301 Series (Continued) * 10-bit slave address mask register (ITMK0/1) Address : 000098H/0000B8H Initial value = > Address : 000099H/0000B9H 15 ENTB R/W 0 7 TM7 R/W 14 RAL R 0 6 TM6 R/W 13 R 1 5 TM5 R/W 1 12 R 1 4 TM4 R/W 1 11 R 1 3 TM3 R/W 1 10 R 1 2 TM2 R/W 1 9 TM9 R/W 1 1 TM1 R/W 1 8 TM8 R/W 1 0 TM0 R/W 1 Initial value = > 1 1 * 7-bit slave address register (ISBA0/1) Address : 00009BH/0000BBH 7 R 6 SA6 R/W 5 SA5 R/W 4 SA4 R/W 0 3 SA3 R/W 0 2 SA2 R/W 0 1 SA1 R/W 0 0 SA0 R/W 0 Initial value = > 0 0 0 * 7-bit slave address mask register (ISMK0/1) Address : 00009AH/0000BAH Initial value = > *Data register (IDAR0/1) Address : 00009DH/0000BDH 15 ENSB R/W 0 14 SM6 R/W 1 13 SM5 R/W 1 12 SM4 R/W 1 11 SM3 R/W 1 10 SM2 R/W 1 9 SM1 R/W 1 8 SM0 R/W 1 7 D7 R/W 6 D6 R/W 0 5 D5 R/W 0 4 D4 R/W 0 3 D3 R/W 0 2 D2 R/W 0 1 D1 R/W 0 0 D0 R/W 0 Initial value = > 0 *Clock control register (ICCR0/1) Address : 00009EH/0000BEH 15 TEST W 14 R 0 13 EN R/W 0 12 CS4 R/W 1 11 CS3 R/W 1 10 CS2 R/W 1 9 CS1 R/W 1 8 CS0 R/W 1 Initial value = > 0 *Clock disable register (IDBL0/1) Address : 00009FH/0000BFH Initial value = > 7 R 0 6 R 0 5 R 0 4 R 0 3 R 0 2 R 0 1 R 0 0 DBL R/W 0 89 MB91301 Series 13. 16 bit Free Run Timer 16-bit free-run timer consists of a 16-bit up counter and a control status register. The timer count value is used as the base timer of output compare and input capture. * The count clock can be selected from four different clocks. * Can be generated the interrupt by the counter over-flow. * Setting the mode enables initialization of counter through compare-match operation with the value of the compare clear register0 in the output compare. 90 MB91301 Series *Block Diagram Interrupt ECLK IVF IVFE STOP MODE CLR CLK1 CLK0 Prescaler F-bus FRCK Clock selector 16-bit Free run Timer (TCDT) Clock To internal circuit (T15 to T00) Comparator0 *Register List 15 T15 14 T14 13 T13 12 T12 11 T11 10 T10 9 T9 8 T8 Timer data register (upper) (TCDT) Timer data register (lower) (TCDT) Timer control status register (lower) (TCCS) 7 T07 7 ECLK 6 T06 6 IVF 5 T05 5 IVFE 4 T04 4 STOP 3 T03 3 MODE 2 T02 2 CLR 1 T01 1 CLK1 0 T00 0 CLK0 91 MB91301 Series 14. Input Capture This module has a function that detects a rising edge, falling edge or both edges and holds a value of the 16-bit free-run timer in a register at the time of detection. It can also generate an interrupt when detecting an edge. The input capture consist of input capture and control registers. Each input capture have the corresponded external input pins. * The valid edge of the external input can be selected from three types : Rising edge Falling edge Both edges * It can generate an interrupt when it detects the valid edge of the external input. 92 MB91301 Series *Block Diagram 16-bit timer count value (T15 to T00) Capture data register ch (0, 2) ICU0, ICU2 input pin Edge detection EG11 R-bus EG31 EG10 EG30 EG01 EG21 EG00 EG20 16-bit timer count value (T15 to T00) Capture data register ch (1, 3) ICU1, ICU3 input pin Edge detection ICP1 ICP3 ICP0 ICP2 ICE1 ICE3 ICE0 ICE2 Interrupt Interrupt 93 MB91301 Series *Register List 15 CP15 14 CP14 13 CP13 12 CP12 11 CP11 10 CP10 9 CP09 8 CP08 Input capture data register (upper) (IPCP) Input capture data register (lower) (IPCP) Capture control register (ICS23) Capture control register (ICS01) 7 CP07 6 CP06 5 CP05 4 CP04 3 CP03 2 CP02 1 CP01 0 CP00 7 ICP3 6 ICP2 5 ICE3 4 ICE2 3 EG31 2 EG30 1 EG21 0 EG20 7 ICP1 6 ICP0 5 ICE1 4 ICE0 3 EG11 2 EG10 1 EG01 0 EG00 94 MB91301 Series 15. Clock Generation Control The internal operating clock is generated as follows in MB91301 series. * Source clock selection : Selects the clock source. * Base clock generation : The base clock is generated by dividing the source clock by 2 or using a PLL. * Generation in each internal block : The base clock is divided to generate the operating clock for each block. 95 MB91301 Series * Block Diagram [Clock generator] DIVR0, 1 register R-bus Selector CPU clock division Peripheral clock division External bus clock division CLKR register X1 Stop control CPU clock (CLKB) Peripheral clock (CLKP) External bus clock (CLKT) tion circuit PLL 1/2 Internal interrupt Internal reset [Stop/sleep controller] Stop state STCR register State transition control circuit Selector X0 Oscilla- Selector Selector SLEEP state Reset F/F Reset F/F Internal reset (RST) Internal reset (INIT) [Reset circuit] INIT pin RSRR register [Watchdog controller] WPR register Watchdog F/F Timebase counter CTBR register Selector Count clock TBCR register Overflow detection F/F Interrupt enable Timebase timer interrupt request 96 MB91301 Series * Register List * RSRR : Reset initiation register/Watchdog timer control register bit Address : 00000480H Initial value (INIT pin) Initial value (INIT) Initial value (RST) * STCR : Standby control register 15 INIT R 1 - X 14 R 0 0 X 13 WDOG R 0 - X 12 R 0 X - 11 SRST R 0 X - 10 R 0 - X 9 WT1 R/W 0 0 0 8 WT0 R/W 0 0 0 bit Address : 00000481H Initial value (INIT pin) Initial value (INIT) Initial value (RST) 7 STOP R/W 0 0 0 6 SLEEP R/W 0 0 0 5 HIZ R/W 1 1 X 4 SRST R/W 1 1 1 3 OS1 R/W 0 X X 2 OS0 R/W 0 X X 1 - - - 0 OSCD1 R/W 1 1 X * TBCR : Timebase counter control register bit Address : 00000482H Initial value (INIT) Initial value (RST) 15 TBIF R/W 0 0 14 TBIE R/W 0 0 13 TBC2 R/W X X 12 TBC1 R/W X X 11 TBC0 R/W X X 10 - - 9 R/W 0 X 8 R/W 0 X SYNCR SYNCS * CTBR : Timebase counter clear register bit Address : 00000483H Initial value (INIT) Initial value (RST) 7 D7 W X X 6 D6 W X X 5 D5 W X X 4 D4 W X X 3 D3 W X X 2 D2 W X X 1 D1 W X X 0 D0 W X X * CLKR : Clock source control register bit Address : 00000484H Initial value (INIT) Initial value (RST) 15 - - 14 R/W 0 X 13 R/W 0 X 12 R/W 0 X 11 - - 10 R/W 0 X 9 R/W 0 X 8 CLKS0 R/W 0 X (Continued) PLL1S2 PLL1S1 PLL1S0 PLL1EN CLKS1 97 MB91301 Series (Continued) * WPR : Watchdog reset generation delay register bit Address : 00000485H Initial value (INIT) Initial value (RST) 7 D7 W X X 6 D6 W X X 5 D5 W X X 4 D4 W X X 3 D3 W X X 2 D2 W X X 1 D1 W X X 0 D0 W X X * DIVR0 : Base clock division setting register 0 bit Address : 00000486H Initial value (INIT) Initial value (RST) 15 B3 R/W 0 X 14 B2 R/W 0 X 13 B1 R/W 0 X 12 B0 R/W 0 X 11 P3 R/W 0 X 10 P2 R/W 0 X 9 P1 R/W 1 X 8 P0 R/W 1 X * DIVR1 : Base clock division setting register 1 bit Address : 00000487H Initial value (INIT) Initial value (RST) 7 T3 R/W 0 X 6 T2 R/W 0 X 5 T1 R/W 0 X 4 T0 R/W 0 X 3 - - 2 - - 1 - - 0 - - - : Changes depending on what triggered the reset. x : Not initialized 98 MB91301 Series ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings (VSS = AVSS = 0 V) Parameter Supply voltage Analog supply voltage Analog reference voltage Input voltage Analog pin input voltage Output voltage "L" level maximum output current "L" level average output current "L" level total maximum output current "L" level total average output current "H" level maximum output current "H" level average output current "H" level total maximum output current "H" level total average output current Power consumption Operating temperature Storage temperature Symbol VCC AVCC AVRH, AVRL VI VIA VOH IOL IOLAV IOL IOLAV IOH IOHAV IOH IOHAV PD Ta TSTG Rating Min VSS - 0.5 VSS - 0.5 VSS - 0.5 VSS - 0.3 VSS - 0.3 VSS - 0.3 0 -50 Max VSS + 4.0 VSS + 4.0 AVCC VCC + 0.3 AVCC + 0.3 VCC + 0.3 10 8 100 50 -10 -4 -50 -20 1000 +70 +150 Unit V V V V V V mA mA mA mA mA mA mA mA mW C C *5 *5 *3 *4 *3 *4 *1 *2 *2 Remarks *1 : VCC must not be lower than VSS - 0.3 V. *2 : AVCC, AVRH and AVRL should not exceed VCC+0.3 V, including at power-on. AVRH and AVRL should not exceed AVCC. Also AVRL should not exceed AVRH. *3 : The maximum output current is the peak value for a single pin. *4 : The average output current is the average current for a single pin over a period of 100ms. *5 : The total average output current is the average current for all pins over a period of 100ms. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 99 MB91301 Series 2. Recommended Operating Conditions (VSS = AVSS = 0 V) Parameter Supply voltage Analog supply voltage Analog reference voltage Operating temperature Symbol VCC AVCC AVRH AVRL Ta Value Min 3.0 VSS + 3 AVSS AVSS 0 Max 3.6 3.6 AVCC AVRH +70 Unit V V V V C Remarks Normal operation <Notes on turning the power on> The maximum power rising slope (V/t) must be 0.05 V/s when the 3 V power supply is turned on. It takes about 100 s until the 2.5 V power supply becomes stable after the 3 V power supply becomes stable. Keep INIT input during that interval. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 100 MB91301 Series 3. DC Characteristics (VCC = 3.0 V to 3.6 V , VSS = AVSS = 0 V, Ta = 0 C to +70 C) Parameter Symbol VIH VIHS VIL VILS VOH VOL Pin name Non-hysteresis input pin Hysteresis input pin Non-hysteresis input pin Hysteresis input pin All output pins All output pins Condition Value Min 2.0 0.8 x VCC VSS VSS Typ Max VCC + 0.3 VCC + 0.3 0.8 0.2 x VCC VCC 0.4 Unit V V V V V V Hysteresis input Hysteresis input Remarks "H" level input voltage "L" level input voltage "H" level output voltage "L" level output voltage Input leak current (Hi-Z output leak current) Pull-up resistance VCC = 3.0 V VCC - 0.4 IOH = -4.0 mA VCC = 3.0 V IOL = 4.0 mA VSS ILI VCC = 3.6 V All input pins* 0.45 V < VI < VCC With pins Pull- VCC = 3.6 V up settings VI = 0.45 V fC = 17 MHz VCC = 3.6 V VCC -5 +5 A RUP 10 25 120 k When operating at : CLKB : 68 MHz mA CLKT : 68 MHz CLKP : 34 MHz (x4 multiplier) When sleeping at : mA CLKP : 34 MHz in sleep mode A In stop mode ICC Power supply current ICCS ICCH Except for VCC VSS AVCC AVSS AVRH AVR 120 150 fC = 17 MHz VCC = 3.6 V Ta = +25 C VCC = 3.6 V 50 200 90 700 Input capacitance CIN 5 15 pF * : Excludes X0, X1, pins with internal pull-up resistor (INIT, TRST), and pins with a pull-up resistor set by PCR. 101 MB91301 Series 4. AC Characteristics (1) Clock Timing Ratings Parameter Clock frequency (1) Clock cycle time Clock frequency (2) Internal operation clock frequency Internal operation clock cycle time Sym- Pin bol name fC tC fC fCP fCPP fCPT tCP tCPP tCPT X0, X1 X0, X1 X0, X1 10 0.78* 0.78* 0.78* 14.7 29.4 14.7 58.8 34 68 34 68 1280* 1280* 1280* ns MHz Condition (VCC = 3.0 V to 3.6 V , VSS = AVSS = 0 V, Ta = 0 C to +70 C) Value Min 12.5 Max 17 Unit MHz Remarks Using PLL (When operating at max internal frequency (68 MHz) = 17 MHz self-oscillation with x4 PLL) Self-oscillation (1/2 division input) MHz CPU MHz Peripherals MHz External bus ns ns ns CPU Peripherals External bus * : Values are for minimum clock frequency (12.5 MHz) input to X0, oscillation circuit uses PLL, and gear ratio = 1/16. * Conditions for measuring the clock timing ratings tC 0.8 VCC Output pin C = 50 pF * Warranted operation range VCC (V) Warranted operation range (Ta = 0 C to +70 C) Power supply 3.6 fCPP is represented by the shaded area. 3.0 0 0.78 34 68 fCP / fCPP (MHz) Internal operation clock 102 MB91301 Series * External/internal clock setting range fcp, fCPT 70 68 MHz 5 multiplier (CPU) 4 multiplier (CPU) 60 50 48 3 multiplier (CPU) 40 fCPP 34 30 5 multiplier, 2 divide (CPU, peripheral) 4 multiplier, 2 divide (CPU, peripheral) 3 multiplier, 2 divide (CPU, peripheral) 4 multiplier, 3 divide (CPU, peripheral) 4 multiplier, 4 divide (CPU, peripheral) 24 22.7 20 17 5 multiplier, 3 divide (CPU, peripheral) 10 5 1/2 divide 0 0 10 12.5 PLL 17 20 30 34 fc MHz Notes : * If using the PLL, input an external clock in the range 12.5 MHz to 17 MHz. * Allow a PLL oscillation stabilization time > 300 s. * Set the gear ratio for the internal clock to be within the values shown in the "(1) Clock Timing Ratings" table. 103 MB91301 Series (2) Clock Output Timing (VCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V, Ta = 0 C to +70 C) Parameter Cycle time SYSCLKSYSCLK SYSCLKSYSCLK Symbol tCYC tCHCL tCLCH Pin name SYSCLK, MCLK SYSCLK, MCLK SYSCLK, MCLK Condition Value Min tCPT 1 tCYC-2.35 2 1 tCYC-2.35 2 Max 1 tCYC+2.65 2 1 tCYC+2.65 2 Unit ns ns ns Remarks *1 *2 *3 tCYC tCHCL VOH tCLCH VOH SYSCLK MCLK VOL *1 : tCYC is the frequency of one clock cycle after gearing. *2 : The following ratings are for the gear ratio set to x 1. For the ratings when the gear ratio is set to between 1/2, 1/4 and 1/8, substitute 1/2, 1/4 or 1/8 for n in the following equation. Min : (1 / 2 x 1 / n) x tCYC - 2.35 Max : (1 / 2 x 1 / n) x tCYC + 2.65 *3 : The following rating are for the gear ratio set to x 1. Min : (1 / 2 x 1 / n) x tCYC - 2.35 Max : (1 / 2 x 1 / n) x tCYC + 2.65 (3) Reset and Tool Reset Input Ratings (VCC = 3.0 V to 3.6 V , VSS = AVSS = 0 V, Ta = 0 C to +70 C) Parameter INIT input time (at power-on) INIT input time ( other than at power-on) INIT input time (recovery from stop) tINTL INIT, TRST Symbol Pin name Condition Value Min 20 + tCP x 5 20 + Max Unit s ns s Remarks tINTL INIT TRST 0.2 VCC 104 MB91301 Series (4) Normal Bus Access Read/Write Operation (VCC = 3.0 V to 3.6 V , VSS = AVSS = 0 V, Ta = 0 C to +70 C) Parameter CS0 to CS7 setup CS0 to CS7 hold Symbol tCSLCH tCHCSH tASCH Pin name SYSCLK, CS0 to CS7 SYSCLK, A23 to A00 WR0 to WR3, A23 to A00 RD, A23 to A00 SYSCLK, A23 to A00 WR0 to WR3, A23 to A00 RD, A23 to A00 A23 to A00, D31 to D00 SYSCLK, WR, WR0 to WR3 WR, WR0 to WR3 WR, WR0 to WR3, D31 to D00 SYSCLK, RD Condition Value Min 3 3 3 4 5 3 tCYC / 2 - 5 tCYC / 2 - 7 Max tCYC / 2 + 4 tCYC / 2 + 4 3 / 2xtCYC - 11 6 6 6 10 tCYC - 10 Unit Remarks ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns * * Address setup tASWL tASRL tCHAX Address hold tWHAX tRHAX Valid address Valid data input time WR0 to WR3 delay time WR0 to WR3 delay time WR0 to WR3 minimum pulse width Data setup WRx WRx Data hold time RD delay time RD delay time RD Valid data input time Data setup RD time RD Data hold time RD minimum pulse width AS setup AS hold UUB/ULB/LUB/LLB set up UUB/ULB/LUB/LLB hold tAVDV tCHWL tCHWH tWLWH tDSWH tWHDX tCHRL tCHRH tRLDV tDSRH tRHDX tRLRH tASLCH tCHASH tBLCH tCHBH tCYC - 5 tCYC 5 RD, D31 to D00 10 0 RD SYSCLK, AS SYSCLK, UUB/ ULB/LUB/LLB tCYC - 5 tCYC / 2 - 6 3 tCYC / 2 - 6 3 * : When the bus is delayed by automatic wait insertion or RDY input, add (tCYC x number of wait cycles) to the rated values. 105 MB91301 Series tCYC BA1 VOH VOH VOH VOH MCLK SYSCLK tASLCH tCHASH VOH AS (LBA) VOL tCSLCH tCHCSH VOH VOL CS0 to CS7 tASCH VOH VOL tCHAX VOH VOL A23 to A00 tCHRL tCHRH tRLRH VOH VOL RD tASRL tRLDV tDSRH tAVDV tRHDX tRHAX D31 to D00 VOH VOL tCHWL tWLWH tCHWH VOH tASWL VOL VOH VOL WR0 to WR3 WR tWHAX tWHDX (at WR-control) tDSWH VOH VOL tBLCH D31 to D00 Write tCHBH VOH VOL WR0 to WR3 (UUB, ULB, LUB, LLB) (at WR-control) 106 MB91301 Series (5) BAA Timing (VCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V, Ta = 0 C to +70 C) Parameter BAA setup BAA hold Symbol tCHBAH tCHBAL Pin name SYSCLK, BAA Condition Value Min tCYC / 2 - 6 3 Max Unit ns ns Remarks tCYC VOH VOH MCLK SYSCLK tCHBAL tCHBAH BAA 107 MB91301 Series (6) Ready Input Timings (VCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V, Ta = 0 C to +70 C) Parameter RDY setup time SYSCLK SYSCLK RDY hold time Symbol tRDYS tRDYH Pin name SYSCLK RDY SYSCLK RDY Condition Value Min 10 0 Max Unit ns ns Remarks tCYC SYSCLK MCLK VOH VOL VOL VOH tRDYS tRDYH tRDYS tRDYH RDY (Wait specified by RDY) VOH VOL VOL VOH RDY (No wait specified by RDY) VOH VOL VOH VOL 108 MB91301 Series (7) Hold Timing (VCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V, Ta = 0 C to +70 C) Parameter BGRNT delay time BGRNT delay time Pin floating BGRNT time BGRNT pin valid time Symbol tCHBGL tCHBGH tXHAL tHAHV Pin name SYSCLK, BGRNT BGRNT, each pins Condition Value Min tCYC - 10 tCYC - 10 Max 6 6 tCYC + 10 tCYC + 10 Unit ns ns ns ns Remarks Note : The time from receiving BRQ to BGRNT changing is one cycle or more. tCYC SYSCLK MCLK VOH VOH VOH VOH BRQ tCHBGL tCHBGH BGRNT tXHAL VOL VOH tHAHV Other pins High-Z 109 MB91301 Series (8) SDRAM Timing (VCC = 3.0 V to 3.6 V , VSS = AVSS = 0 V, Ta = 0 C to +70 C) Parameter Output clock cycle time "H" level clock pulse width "L" level clock pulse width MCLKO output delay time Output hold time MCLKO output delay time Output hold time MCLKO output delay time Output hold time MCLKO output delay time Output hold time MCLKO output delay time Output hold time MCLKO output delay time Output hold time MCLKO output delay time Output hold time MCLKO output delay time Output hold time Data input setup time Data input hold time Symbol tCYCSD tCHSD tCLSD tODSDCKE tOHSDCKE tODSDRAS tOHSDRAS tODSDCAS tOHSDCAS tODSDWE tOHSDWE tODSDCS tOHSDCS tODSDA tOHSDA tODSDDQM tOHSDDQM tODSDD tOHSDD tISSDD tIHSDD D00 to D31 DQMUU, DQMUL, DQMLU, DQMLL D00 to D31 A00 to A15 CS6, CS7 SWE SCAS SRAS MCLKE MCLK Pin name Condition Value Min 5 5 2 2 2 2 2 2 2 2 4 2 Max 68 11 11 11 11 11 11 11 11 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Remarks 110 MB91301 Series tCYCSD MCLKO tCHSD tCLSD MCLKO MCLKE SRAS SCAS SWE CS6 CS7 A00 to A15 DQMUU DQMUL DQMLU DQMLL tODSDCKE tODSDRAS tODSDCAS tODSDWE tODSDCS tODSDA tODSDDQM tOHSDCKE tOHSDRAS tOHSDCAS tOHSDWE tOHSDCS tOHSDA tOHSDDQM tODSDD D00 to D31 output tOHSDD D00 to D31 input tISSDD tIHSDD 111 MB91301 Series (9) UART Timing (VCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V, Ta = 0 C to +70 C) Parameter Serial clock cycle time SCK SO delay time Valid SI SCK SCK valid SIN hold time Serial clock "H" pulse width Serial clock "L" pulse width SCK SOT delay time Valid SINSCK SCK valid SIN hold time Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX Pin name SCK0 to SCK2 SCK0 to SCK2, SOT0 to SOT2 SCK0 to SCK2, SIN0 to SIN2 SCK0 to SCK2, SIN0 to SIN2 SCK0 to SCK2 SCK0 to SCK2 SCK0 to SCK2, SOT0 to SOT2 SCK0 to SCK2, SIN0 to SIN2 SCK0 to SCK2, SIN0 to SIN2 External shift clock mode Internal shift clock mode Condition Value Min 8 tCYCP -80 100 60 4 tCYCP 4 tCYCP 60 60 Max +80 150 Unit ns ns ns ns ns ns ns ns ns Remarks Notes : * These are the AC ratings for CLK synchronous mode. * tCYCP is the peripheral clock cycle time. 112 MB91301 Series * Internal shift clock mode tSCYC SCK0 to SCK2 VOH VOL tSLOV VOL SOT0 to SOT2 VOH VOL tIVSH VOH VOL tSHIX VOH VOL SIN0 to SIN2 * External shift clock mode tSLSH tSHSL VOH VOL tSLOV VOL VOL SCK0 to SCK2 SOT0 to SOT2 VOH VOL tIVSH VOH VOL tSHIX VOH VOL SIN0 to SIN2 113 MB91301 Series (10) Reload Timer Clock and PPG Timer Input Timings (VCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V, Ta = 0 C to +70 C) Parameter Symbol tTIWH tTIWL Pin name TIN0 to TIN2, PPG0 to PPG3, TRG0 to TRG3 Condition Value Min 2 tCYCP* Max Unit Remarks Input pulse width ns * : tCYCP is the peripheral clock cycle time. TIN0 to TIN2 PPG0 to PPG3 TRG0 to TRG3 VIH VIH VIL tTIWH tTIWL VIL (11) Trigger Input Timing (VCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V, Ta = 0 C to +70 C) Parameter A/D activation trigger input time Symbol tATGL Pin name ATG Condition Value Min 5 tCYCP* Max Unit ns Remarks * : tCYCP is the peripheral clock cycle time. tATGL ATG VIL VIL 114 MB91301 Series (12) DMA Controller Timing (VCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V, Ta = 0 C to +70 C) [ For edge detection ] (Block/step transfer mode, burst transfer mode) Value SymParameter Pin name Condition Unit Remarks bol Min Max DREQ input pulse width tDRWL DREQ 0, DREQ1 2 tCYC ns Note : When fCPT > fCP, tCYC becomes same as tCP . [ For level detection ] (Demand transfer mode) Parameter DSTP setup time DSTP hold time Symbol tDREQS tDREQH Pin name SYSCLK, DREQ 0, DREQ1 SYSCLK, DREQ 0, DREQ1 Condition Value Min 10 0.0 ns Max Unit ns Remarks [ For all operation modes ] Parameter DACK delay time DEOP delay time IORD delay time IOWR delay time Symbol tCLDL tCLDH tCLEL tCLEH tCLIRL tCLIRH tCLIWL tCLIWH Pin name SYSCLK, DACK 0, DACK1 SYSCLK, DEOP 0, DEOP1 SYSCLK, IORD SYSCLK, IOWR Condition Value Min Max 10 10 10 10 10 10 10 10 Unit ns ns ns ns Remarks 115 MB91301 Series tCYC SYSCLK MCLK VOH VOL VOL VOH VOL tCLDL tCLDH VOH DACK0, DACK1 tCLEL VOL tCLEH VOH DEOP0, DEOP1 tCLIRL VOL tCLIRH VOH VOL tCLIWL tCLIWH VOH IORD IOWR VOL tDRWL tDREQS tDREQH VOH VOL DREQ0, DREQ1 DREQ0, DREQ1 VOH VOL 116 MB91301 Series (13) I2C Timing * At master mode operation (AVCC = VCC = 3.3 0.3 V, AVSS = VSS = 0.0 V, Ta = 0 C to +70 C) Parameter SCL clock frequency Symbol fSCL Pin SCL0, SCL1 SCL0, SCL1 SCL0, SCL1 SDA0, SDA1 SCL0, SCL1, SDA0, SDA1 SCL0, SCL1, SDA0, SDA1 SCL0, SCL1, SDA0, SDA1 SCL0, SCL1, SDA0, SDA1 R = 1 k, C = 50 pF*4 Conditions Typical mode Min 0 4.7 4.0 4.7 4.7 Max 100 5 x M*1 Fast mode*3 Min 0 1.3 0.6 1.3 0.6 Max 400 5 x M*1 Unit kHz s s s ns s After that, the s first clock pulse is generated. s s ns Remarks "L" period of SCL clock tLOW "H" period of SCL clock tHIGH BUS free time between "STOP condition" and "START condition" SCLSDA output delay time Setup time of "repeat START condition" SCLSDA Hold time of "repeat START condition" SDASCL Setup time of "STOP condition" SCLSDA SDA data input hold time (vs. SCL) SDA data input setup time (vs. SCL) tBUS tHDDAT tSUSTA tHDSTA 4.0 0.6 tSUSTO 4.0 2 x M*1 250 0.6 2 x M*1 100*2 tHDDAT SDA0, SDA1 tSUDAT SDA0, SDA1 *1 : M = resource clock cycle (ns) *2 : A high-speed mode I2C bus device can be used for a standard mode I2C bus system as long as the device satisfies a requirement of "tSUDAT 250 ns". When a certain device does not extend the "L" period of the SCL signal, the next data must be output to the SDA line within 1250 ns (maximum SDA/SCL rise time + tSUDATA) in which the SCL line is released. *3 : For use at over 100 kHz, set the resource clock frequency to at least 6 MHz. *4 : R and C represent the pull-up resistor and load capacitor of the SCL and SDA output lines. 117 MB91301 Series * At slave mode operation (AVCC = VCC = 3.3 0.3 V, AVSS = VSS = 0.0 V, Ta = 0 C to +70 C) Parameter SCL clock frequency Symbol fSCL Pin SCL0, SCL1 SCL0, SCL1 SCL0, SCL1 SDA0, SDA1 SCL0, SCL1, SDA0, SDA1 SCL0, SCL1, SDA0, SDA1 SCL0, SCL1, SDA0, SDA1 SCL0, SCL1, SDA0, SDA1 R = 1 k, C = 50 pF*4 Conditions Typical mode Min 0 4.7 4.0 4.7 4.7 Max 100 5 x M*1 Fast mode*3 Min 0 1.3 0.6 1.3 0.6 Max 400 5 x M*1 Unit kHz s s s ns s After that, the s first clock pulse is generated. s s ns Remarks "L" period of SCL clock tLOW "H" period of SCL clock tHIGH BUS free time between "STOP condition" and "START condition" SCLSDA output delay time Setup time of "repeat START condition" SCLSDA Hold time of "repeat START condition" SDASCL Setup time of "STOP condition" SCLSDA SDA data input hold time (vs. SCL) SDA data input setup time (vs. SCL) tBUS tHDDAT tSUSTA tHDSTA 4.0 0.6 tSUSTO 4.0 2x M*1 250 0.6 2x M*1 100*2 tHDDAT SDA0, SDA1 tHDSTA SDA0, SDA1 *1 : M = resource clock cycle (ns) *2 : A high-speed mode I2C bus device can be used for a standard mode I2C bus system as long as the device satisfies a requirement of "tSUDAT 250 ns". When a certain device does not extend the "L" period of the SCL signal, the next data must be output to the SDA line within 1250 ns (maximum SDA/SCL rise time + tSUDATA) in which the SCL line is released. *3 : For use at over 100 kHz, set the resource clock frequency to at least 6 MHz. *4 : R and C represent the pull-up resistor and load capacitor of the SCL and SDA output lines. SDA tBUS VOH VOL tLOW tHDSTA VOH SCL VOL tHDSTA tHDDAT tHIGH fSCL tSUDAT tSUSTA tSUSTO 118 MB91301 Series 5. Electrical Characteristics for the A/D Converter (VCC = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V, AVRH = 3.0 V to 3.6 V , Ta = 0 C to +70 C) Parameter Resolution Total error Linearity error Differential linearity error Zero transition error Full-scale transition error Symbol VOT VFST Pin name AN0 to AN3 AN0 to AN3 Value Min -8.5 -3.0 -2.5 -8.0 AVRH - 8.0 4.1 s machine clock (CLKP) 34 MHz at operating AVss AVss Typ +0.5 Max 10 +8.5 +3.0 +2.5 +8.0 Unit BIT LSB LSB LSB LSB LSB AVRH - 1.5 AVRH + 8.0 Conversion time*1 s Analog port input current Analog input voltage Reference voltage Power supply current Reference voltage supply current Variation between channels IAIN VAIN IA IAH*2 IR IRH* 2 AN0 to AN3 AN0 to AN3 AVRH AVCC AVRH AN0 to AN3 0.1 0.6 0.6 10 AVRH AVCC 2 10 2 10 5 A V V mA A mA A LSB *1 : For VCC = AVCC = 3.0 V to 3.6 V , machine clock = 34 MHz *2 : Current when A/D converter not operating and CPU in stop mode (VCC = AVCC = AVRH = 3.6 V) Notes : * The relative error increases as AVRH becomes smaller. * Ensure that the output impedance of the external circuit connected to the analog input meets the following condition : Output impedance of external circuit < 7 k If the output impedance of the external circuit is too high, the analog voltage sampling time may be too short. 119 MB91301 Series * About the external impedance of the analog input and its sampling time * A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling time, the analog voltage charged to the internal sampling and hold capacitor is insufficient, adversely affecting A/D conversion precision. * Analog input equivalent circuit R Analog input C Comparator During sampling : ON MB91302A Note : The values are reference. * To satisfy the A/D conversion precision standard, consider the relationship between the external impedance and minimum sampling time and either adjust the resistor value and operating frequency or decrease the external impedance so that the sampling time is longer than the minimum value. * The relationship between the external impedance and minimum sampling time (External impedance = 0 k to 100 k) MB91302A 100 90 80 70 60 50 40 30 20 10 0 0 5 10 15 20 25 30 35 20 18 16 14 12 10 8 6 4 2 0 0 1 2 3 4 5 6 7 8 R C 8.1 k (Max) 10.0 pF (Max) (External impedance = 0 k to 20 k) MB91302A External impedance (k) External impedance (k) Minimum sampling time (s) Minimum sampling time (s) * If the sampling time cannot be sufficient, connect a capacitor of about 0.1 F to the analog input pin. * About errors As |AVRH - AVSS| becomes smaller, values of relative errors grow larger. 120 MB91301 Series 6. Power-on ratings Parameter Power rise time Power start time Power end voltage Power shutdown time Symbol tr Voff Von toff Value Min 2.0 1 Max 38 0.1 Unit ms V V ms Remarks Tilt = 0.05 V / ms tr toff Von VCC Voff 121 MB91301 Series PIN STATUS IN EACH CPU STATE * Terms used in the pin status list * Input ready Indicates that the input function can be used. * Input 0 fixed Indicates that the input level has been internally fixed to be 0 to prevent leakage when the input is released. * Output Hi-Z Indicates to put the pin in a high impedance state with the pin driving transistor disabled for driving. * Output held Indicates the output in the output state existing immediately before this mode is established. If the device enters this mode with an internal output peripheral operating or while serving as an output port, the output is performed by the internal peripheral or the port output is maintained, respectively. * Previous state held When the device serves for output or input immediately before entering this mode, the device maintains the output or is ready for the input, respectively. 122 MB91301 Series * Pin Status List (External bus : 32 bit bus width) Pin no. Port name Specified function name D11 to D15 D16 to D23 D24 to D31 Function name Bus width 32 bit D11 to D15 D16 to D23 D24 to D31 At initialization (INIT) Function name Bus width 8 bit P13 to P17 P20 to P27 D24 to D31 Output Hi-Z Input ready Stop mode Sleep mode HIZ = 0 HIZ = 1 Bus released (BGRNT) CS shared CS not shared Initial value 1 to 5 8 to 15 18 to 25 P13 to P17 P20 to P27 P30 to P37 P : Previous P : Previous state held state held F : Output F : Output held or held or Hi-Z Hi-Z P : Previous state held F : RDY input Output Hi-Z/ input 0 fixed Output Hi-Z Output Hi-Z 28 P80 RDY P80 P80 P : Previous P : Previous state held state held F : RDY input F : RDY input L output Output Hi-Z/ input 0 fixed L output 29 P81 BGRNT P81 P81 Output Hi-Z Input ready P : Previous state held Previous F : H output state held P : Previous state held F : BRQ input invalid 30 P82 BRQ P82 P82 BRQ input BRQ input 31 32 33 34 35 P83 P84 P85 P86 P87 RD RD RD DQMUU/WR0 DQMUU/WR0 DQMUU/WR0 DQMUL/WR1 DQMLU/WR2 DQMLL/WR3 DQMUL/WR1 DQMLU/WR2 DQMLL/WR3 P85 P86 P87 H output P : Previous Previous state held state held F : H output Output Hi-Z Previous state held F : H output 36 P90 SYSCLK SYSCLK SYSCLK P : Previous Asserted state held : L output F : SYSCLK Negated output : CLK output H output F : L output P : Previous state held F : H or L output F : L output Output Hi-Z/ input 0 fixed F : Output Hi-Z F : CLK output F : CLK output 37 P91 MCLKE MCLKE MCLKE Output Hi-Z H output 38 P92 MCLK MCLK MCLK Asserted P : Previous P : Previous F : Output : L output state held state held Hi-Z Negated F : H output F : H output : CLK output Output Hi-Z Input ready Output Hi-Z Input ready Output Hi-Z Input ready Previous state held Previous state held Output Hi-Z Output Hi-Z Output Hi-Z Output Hi-Z/ input 0 fixed Output Hi-Z F : CLK output Port Function F : H output 39 P93 SRAS/LBA/ AS P93 P93 Port Function Output Hi-Z 40 P94 P94 P94 P : Previous state held H output F : H output P : Previous state held H output F : H output P : Previous state held Previous state held F : SWE output 41 P95 SCAS/BAA P95 P95 Output Hi-Z H output 42 P96 SWE/WR P96 P96 Output Hi-Z Input ready Output Hi-Z Previous state held 45 to 52 55 to 62 64 to 67 68 69 70 71 76 to 79 81 82 83 84 P40 to P47 P50 to P57 P60 to P63 P64 P65 P66 P67 PG0 PG1 PG2 PG3 A00 to A07 A08 to A15 A16 to A19 A20/SDA0 A21/SCL0 A22/SDA1 A23/SCL1 AN3 to AN0 INT0/ICU0 INT1/ICU1 INT2/ICU2 INT3/ICU3 A00 to A07 A08 to A15 A16 to A19 A20 A21 A22 A23 AN3 to AN0 PG0 PG1 PG2 PG3 A00 to A07 A08 to A15 A16 to A19 A20 A21 A22 A23 AN3 to AN0 PG0 PG1 PG2 PG3 Output Hi-Z Input ready P : Previous P : Previous P : Output Hi-Z state held state held F : Input F : Input F : Normal ready ready operation Normal operation Normal operation input invalid Previous state held input invalid input invalid Previous state held Previous state held FF output P : Previous state held The same as stated left F : Address output Output Hi-Z/ input 0 fixed Output Hi-Z Output Hi-Z (Continued) 123 MB91301 Series (Continued) At initialization (INIT) Pin no. Port name Specified function name Function name Bus width 32 bit PG4 PG5 PG6 PG7 PJ0 PJ1 PJ2 PJ3 PJ4 PJ5 PJ6 PJ7 PH0 PH1 PH2 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 CS0 CS1 CS2 CS3 CS4 CS5 CS6 CS7 D00 to D07 D08 to D10 Stop mode Sleep mode Bus released (BGRNT) HIZ = 0 HIZ = 1 CS shared CS not shared Function name Bus width 8 bit PG4 PG5 PG6 PG7 PJ0 PJ1 PJ2 PJ3 PJ4 PJ5 PJ6 PJ7 PH0 PH1 PH2 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 CS0 CS1 CS2 CS3 Initial value 85 86 87 88 90 91 92 93 94 95 96 97 98 99 100 103 104 105 106 107 108 109 110 122 123 124 125 126 127 128 129 PG4 PG5 PG6 PG7 PJ0 PJ1 PJ2 PJ3 PJ4 PJ5 PJ6 PJ7 PH0 PH1 PH2 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 INT4/ATG/ FRCK INT5/SIN2 INT6/SOT2 INT7/SCK2 SIN0 SOT0 SCK0 SIN1 SOT1 SCK1 PPG0 TRG0 TIN0 TIN1/PPG3 TIN2/TRG3 DREQ0 DACK0 DEOP0 DREQ1 DACK1/TRG1 DEOP1/PPG1 IOWR IORD CS0 CS1 CS2 CS3 CS4/TRG2 CS5/PPG2 CS6 CS7 D00 to D07 D08 to D10 Output Hi-Z Input ready P : Previous P : Previous P : Output Hi-Z state held state held F : Input F : Input F : Normal ready ready operation Normal operation Normal operation Output Hi-Z Input ready P : Previous state held Previous state held F : Normal operation Output HiZ/input 0 fixed Normal operation Normal operation Output Hi-Z Input ready P : Previous state held Previous state held F : Normal operation Output HiZ/input 0 fixed Normal operation Normal operation Output Hi-Z Input ready P : Previous state held F : Normal operation Previous state held Output HiZ/input 0 fixed Normal operation Normal operation H output CS4 CS5 CS6 CS7 P00 to P07 P10 to P12 Output Hi-Z Input ready H output H output Output Hi-Z F : SREN = F : SREN = 0:H 0:H output, output, SREN = SREN = 1 : Out1 : Output Hi-Z put Hi-Z 132 to 139 P00 to P07 142 to 144 P10 to P12 P : Previous P : Previous state held Output Histate held Z/input 0 F : Output F : Output fixed held or held or Hi-Z Hi-Z Output Hi-Z Output Hi-Z P : General-purpose port selected, F : Specified function selected Notes : * The bus width is determined after a mode vector fetch. * The bus width at initialization time is 8 bits. 124 MB91301 Series * Pin Status List (External bus : 16 bit bus width) Pin no. Port name Specified function name D11 to D15 D16 to D23 D24 to D31 Function name Bus width 16 bit P13 to P17 D16 to D23 D24 to D31 At initialization (INIT) Function name Bus width 8 bit P13 to P17 P20 to P27 D24 to D31 Output Hi-Z Input ready Stop mode Sleep mode HIZ = 0 HIZ = 1 Bus released (BGRNT) CS shared CS not shared Initial value 1 to 5 8 to 15 18 to 25 P13 to P17 P20 to P27 P30 to P37 P : Previous state held F : Output held or Hi-Z P : Previous state held Output HiZ/input 0 F : Output fixed held or Hi-Z Output Hi-Z Output Hi-Z 28 P80 RDY P80 P80 P : Previous state held F : RDY input P : Previous state held F : RDY input Previous state held Output HiZ/input 0 fixed L output P : Previous state held F : RDY input L output 29 P81 BGRNT P81 P81 Output Hi-Z Input ready P : Previous state held F : H output P : Previous state held F : BRQ input invalid 30 P82 BRQ P82 P82 BRQ input BRQ input 31 32 33 34 35 P83 P84 P85 P86 P87 RD DQMUU/WR0 DQMUL/WR1 DQMLU/WR2 DQMLL/WR3 RD DQMUU/WR0 DQMUL/WR1 P86 P87 RD DQMUU/WR0 P85 P86 P87 H output P : Previous Previous state held state held F : H output Output Hi-Z Output Hi-Z F : H output 36 P90 SYSCLK SYSCLK SYSCLK P : Previous P : Previous Asserted state held state held : L output F : SYSCLK F : H or L Negated output output : CLK output H output F : L output F : L output Output HiZ/input 0 fixed F : Output Hi-Z F : CLK output F : CLK output 37 P91 MCLKE MCLKE MCLKE Output Hi-Z H output 38 P92 MCLK MCLK MCLK Asserted P : Previous P : Previous F : Output : L output state held state held Hi-Z Negated F : H output F : H output : CLK output Output Hi-Z Input ready Output Hi-Z Input ready Output Hi-Z Input ready Previous state held P : Previous state held F : H output Previous state held H output Previous state held Output Hi-Z F : CLK output 39 P93 SRAS/LBA/ AS P93 P93 Output Hi-Z Output Hi-Z 40 P94 P94 P94 Output Hi-Z Output Hi-Z F : H output 41 P95 SCAS/BAA P95 P95 P : Previous state held H output F : H output P : Previous state held Previous F : SWE out- state held put Output Hi-Z Output Hi-Z H output 42 P96 SWE/WR P96 P96 Output Hi-Z Input ready Output HiZ/input 0 fixed Output Hi-Z Previous state held 45 to 52 55 to 62 64 to 67 68 69 70 71 76 to 79 P40 to P47 P50 to P57 P60 to P63 P64 P65 P66 P67 A00 to A07 A08 to A15 A16 to A19 A20/SDA0 A21/SCL0 A22/SDA1 A23/SCL1 AN3 to AN0 A00 to A07 A08 to A15 A16 to A19 A20 A21 A22 A23 AN3 to AN0 A00 to A07 A08 to A15 A16 to A19 A20 A21 A22 A23 AN3 to AN0 input invalid Previous state held input invalid input invalid Previous state held Previous state held FF output P : Previous state held F : Address output The same as stated left Output HiZ/input 0 fixed Output Hi-Z Output Hi-Z (Continued) 125 MB91301 Series (Continued) Port name Specified function name Function name Bus width 16 bit PG0 At initialization (INIT) Function name Bus width 8 bit PG0 Stop mode Sleep mode HIZ = 0 HIZ = 1 Pin no. Bus released (BGRNT) CS shared Normal operation Initial value CS not shared Normal operation 81 PG0 INT0/ICU0 Output Hi-Z Input ready P : Previous P : Previous P : Output Hi-Z state held state held F : Input F : Input F : Normal ready ready operation 82 83 84 85 86 87 88 90 91 92 93 94 95 96 97 98 99 100 103 104 105 106 107 108 109 110 122 123 124 125 126 127 128 129 PG1 PG2 PG3 PG4 PG5 PG6 PG7 PJ0 PJ1 PJ2 PJ3 PJ4 PJ5 PJ6 PJ7 PH0 PH1 PH2 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 INT1/ICU1 INT2/ICU2 INT3/ICU3 INT4/ATG/ FRCK INT5/SIN2 INT6/SOT2 INT7/SCK2 SIN0 SOT0 SCK0 SIN1 SOT1 SCK1 PPG0 TRG0 TIN0 TIN1/PPG3 TIN2/TRG3 DREQ0 DACK0 DEOP0 DREQ1 DACK1/TRG1 DEOP1/PPG1 IOWR IORD CS0 CS1 CS2 CS3 CS4/TRG2 CS5/PPG2 CS6 CS7 D00 to D07 D08 to D10 PG1 PG2 PG3 PG4 PG5 PG6 PG7 PJ0 PJ1 PJ2 PJ3 PJ4 PJ5 PJ6 PJ7 PH0 PH1 PH2 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 CS0 CS1 CS2 CS3 CS4 CS5 CS6 CS7 P00 to P07 P10 to P12 PG1 PG2 PG3 PG4 PG5 PG6 PG7 PJ0 PJ1 PJ2 PJ3 PJ4 PJ5 PJ6 PJ7 PH0 PH1 PH2 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 CS0 CS1 CS2 CS3 CS4 CS5 CS6 CS7 P00 to P07 P10 to P12 Output Hi-Z Input ready P : Previous P : Previous state held Output state held Hi-Z/input 0 F : Output F : Output fixed held or held or Hi-Z Hi-Z H output H output H output F : SREN = F : SREN = 0:H 0:H output, output, Output Hi-Z SREN = SREN = 1 : Out1 : Output Hi-Z put Hi-Z Output Hi-Z Input ready P : Previous state held Previous state held F : Normal operation Output Hi-Z/input 0 fixed Normal operation Normal operation Output Hi-Z Input ready P : Previous state held Previous state held F : Normal operation Output Hi-Z/input 0 fixed Normal operation Normal operation Output Hi-Z Input ready P : Previous state held Previous state held F : Normal operation Output Hi-Z/input 0 fixed Normal operation Normal operation Output Hi-Z Input ready P : Previous P : Previous P : Output Hi-Z state held state held F : Input F : Input F : Normal ready ready operation Normal operation Normal operation 132 to 139 P00 to P07 142 to 144 P10 to P12 Output Hi-Z Output Hi-Z P : General-purpose port selected, F : Specified function selected Notes : * The bus width is determined after a mode vector fetch. * The bus width at initialization time is 8 bits. 126 MB91301 Series * Pin Status List (External bus : 8 bit bus width) Pin no. Port name Specified function name D11 to D15 D16 to D23 D24 to D31 Function name Bus width 8 bit P13 to P17 P20 to P27 D24 to D31 At initialization (INIT) Function name Bus width 8 bit P13 to P17 P20 to P27 D24 to D31 Output Hi-Z Input ready Stop mode Sleep mode HIZ = 0 HIZ = 1 Bus released (BGRNT) CS shared CS not shared Initial value 1 to 5 8 to 15 18 to 25 P13 to P17 P20 to P27 P30 to P37 P : Previous P : Previous state held Output state held Hi-Z/input F : Output F : Output held 0 fixed held or or Hi-Z Hi-Z P : Previous state held F : RDY input P : Previous state held F : H output P : Previous state held F : BRQ input invalid Output Hi-Z Output Hi-Z 28 P80 RDY P80 P80 P : Previous P : Previous state state held held F : RDY F : RDY input input Previous state held Output Hi-Z/input 0 fixed L output L output 29 P81 BGRNT P81 P81 Output Hi-Z Input ready 30 P82 BRQ P82 P82 BRQ input BRQ input 31 32 33 34 35 P83 P84 P85 P86 P87 RD DQMUU/WR0 DQMUL/WR1 DQMLU/WR2 DQMLL/WR3 RD DQMUU/WR0 P85 P86 P87 RD DQMUU/WR0 P85 P86 P87 H output P : Previous state held F : H output Previous state held Output Hi-Z Output Hi-Z F : H output 36 P90 SYSCLK SYSCLK SYSCLK P : Previous Asserted state held : L output F : SYSCLK Negated output : CLK output H output F : L output P : Previous Output state held Hi-Z/input F : H or L 0 fixed output F : L output F : Output Hi-Z F : CLK output F : CLK output 37 P91 MCLKE MCLKE MCLKE Output Hi-Z H output 38 P92 MCLK MCLK MCLK Asserted P : Previous : L output state held Negated F : H output : CLK output Output Hi-Z Input ready Output Hi-Z Input ready Output Hi-Z Input ready Output Hi-Z Input ready P : Previous F : Output state held Hi-Z F : H output Previous state held Output Hi-Z Output Hi-Z Output Hi-Z/input 0 fixed Output Hi-Z F : CLK output 39 P93 SRAS/LBA/AS P93 P93 Previous state Previous held state held P : Previous state held F : H output P : Previous state held F : H output H output Output Hi-Z Output Hi-Z 40 P94 P94 P94 Output Hi-Z F : H output 41 P95 SCAS/BAA P95 P95 H output Output Hi-Z H output 42 45 to 52 55 to 62 64 to 67 68 69 70 71 76 to 79 P96 P40 to P47 P50 to P57 P60 to P63 P64 P65 P66 P67 SWE/WR A00 to A07 A08 to A15 A16 to A19 A20/SDA0 A21/SCL0 A22/SDA1 A23/SCL1 AN3 to AN0 P96 A00 to A07 A08 to A15 A16 to A19 A20 A21 A22 A23 AN3 to AN0 P96 A00 to A07 A08 to A15 A16 to A19 A20 A21 A22 A23 AN3 to AN0 P : Previous Previous state held state held F : SWE output Output Hi-Z Previous state held FF output P : Previous state held F : Address output Output The same as Hi-Z/input stated left 0 fixed Output Hi-Z Output Hi-Z input invalid Previous state input invalid held input invalid Previous state held Previous state held Normal operation 81 PG0 INT0/ICU0 PG0 PG0 Output Hi-Z Input ready P : Previous P : Output P : Previous Hi-Z Normal state held state held F : Input operation F : Normal op- F : Input ready ready eration (Continued) 127 MB91301 Series (Continued) Port name Specified function name Function name Bus width 8 bit PG1 PG2 PG3 PG4 PG5 PG6 PG7 PJ0 PJ1 PJ2 PJ3 PJ4 PJ5 PJ6 PJ7 PH0 PH1 PH2 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 CS0 CS1 CS2 CS3 CS4 CS5 CS6 CS7 P00 to P07 P10 to P12 At initialization (INIT) Function name Bus width 8 bit PG1 PG2 PG3 PG4 PG5 PG6 PG7 PJ0 PJ1 PJ2 PJ3 PJ4 PJ5 PJ6 PJ7 PH0 PH1 PH2 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 CS0 CS1 CS2 CS3 H output H output Output Hi-Z Input ready Output Hi-Z Input ready Output Hi-Z Input ready Output Hi-Z Input ready Stop mode Sleep mode Pin no. Bus released (BGRNT) CS shared CS not shared Initial value HIZ = 0 HIZ = 1 82 83 84 85 86 87 88 90 91 92 93 94 95 96 97 98 99 100 103 104 105 106 107 108 109 110 122 123 124 125 126 127 128 129 PG1 PG2 PG3 PG4 PG5 PG6 PG7 PJ0 PJ1 PJ2 PJ3 PJ4 PJ5 PJ6 PJ7 PH0 PH1 PH2 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 INT1/ICU1 INT2/ICU2 INT3/ICU3 INT4/ATG/ FRCK INT5/SIN2 INT6/SOT2 INT7/SCK2 SIN0 SOT0 SCK0 SIN1 SOT1 SCK1 PPG0 TRG0 TIN0 TIN1/PPG3 TIN2/TRG3 DREQ0 DACK0 DEOP0 DREQ1 DACK1/TRG1 DEOP1/PPG1 IOWR IORD CS0 CS1 CS2 CS3 CS4/TRG2 CS5/PPG2 CS6 CS7 D00 to D07 D08 to D10 P : Previous P : Previous P : Output Hi-Z state held state held F : Input F : Input F : Normal ready ready operation Normal operation Normal operation P : Previous state held Previous F : Normal state held operation Output Normal Hi-Z/input 0 operation fixed Normal operation P : Previous state held Previous state held F : Normal operation Output Normal Hi-Z/input 0 operation fixed Normal operation P : Previous state held Previous state held F : Normal operation Output Normal Hi-Z/input 0 operation fixed Normal operation H output CS4 CS5 CS6 CS7 P00 to P07 P10 to P12 Output Hi-Z Input ready F : SREN = F : SREN = 0:H 0:H output, output, Output Hi-Z SREN = SREN = 1 : Out1 : Output Hi-Z put Hi-Z 132 to 139 P00 to P07 142 to 144 P10 to P12 P : Previous P : Previous state held Output state held Hi-Z/input 0 Output Hi-Z Output Hi-Z F : Output F : Output fixed held or held or Hi-Z Hi-Z P : General-purpose port selected, F : Specified function selected Notes : * The bus width is determined after a mode vector fetch. * The bus width at initialization time is 8 bits. 128 MB91301 Series * Pin Status List (Single chip mode) At initialization (INIT) Pin no. Port name Specified function name Function name Bus width 8 bit P13 to P17 P20 to P27 P30 to P37 P80 P81 P82 P83 P84 P85 P86 P87 P90 P91 P92 P93 P94 P95 P96 P40 to P47 Output Hi-Z P50 to P57 P60 to P63 P64 P65 P66 P67 AN0 to AN3 PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 PJ0 PJ1 PJ2 PJ3 PJ4 PJ5 Output Hi-Z/ input 0 fixed Output Hi-Z/ Input ready Previous state held P : Previous state held F : Input ready Previous state held P : Output Hi-Z F : Input ready Input invalid Input invalid input invalid Previous state held Output Hi-Z Output Hi-Z/ Input ready Output Hi-Z/ input 0 fixed Previous state held Previous state held Stop mode Sleep mode HIZ Initial value Internal ROM mode vector (MD2-0 = 000) =0 HIZ = 1 1 to 5 8 to 15 18 to 25 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 45 to 52 55 to 62 64 to 67 68 69 70 71 76 to 79 81 82 83 84 85 86 87 88 90 91 92 93 94 95 P13 to P17 P20 to P27 P30 to P37 P80 P81 P82 P83 P84 P85 P86 P87 P90 P91 P92 P93 P94 P95 P96 P40 to P47 P50 to P57 P60 to P63 P64 P65 P66 P67 PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 PJ0 PJ1 PJ2 PJ3 PJ4 PJ5 SRAS SCAS/BAA SWE/WR SDA0 SCL0 SDA1 SCL1 AN0 to AN3 INT0/ICU0 INT1/ICU1 INT2/ICU2 INT3/ICU3 INT4/ATG/FRCK INT5/SIN2 INT6/SOT2 INT7/SCK2 SIN0 SOT0 SCK0 SIN1 SOT1 SCK1 Previous state held Output Hi-Z Previous state held Output Hi-Z (Continued) 129 MB91301 Series (Continued) At initialization (INIT) Pin no. Port name Specified function name Function name Bus width 8 bit PJ6 PJ7 PH0 PH1 PH2 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 P00 to P07 P10 to P12 Output Hi-Z/ Input ready Previous state held Previous state held Output Hi-Z/ input 0 fixed Stop mode Sleep mode HIZ Initial value Internal ROM mode vector (MD2-0 = 000) =0 HIZ = 1 96 97 98 99 100 103 104 105 106 107 108 109 110 122 123 124 125 126 127 128 129 132 to 139 142 to 144 PJ6 PJ7 PH0 PH1 PH2 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 P00 to P07 P10 to P12 PPG0 TRG0 TIN0 TIN1/PPG3 TIN2/TRG3 TRG1 PPG1 TRG2 PPG2 P : General-purpose port selected, F : Specified function selected Notes : * The bus width is determined after a mode vector fetch. * The bus width at initialization time is 8 bits. 130 MB91301 Series EXAMPLE CHARACTERISTICS ICC - Internal frequency (PLL On) External VCC = 3.6 V, Ta = + 25 C 140 120 ICC - External VCC (PLL On) Internal frequency = 68 MHz, Ta = + 25 C 140 120 ICC [mA] ICC [mA] 100 80 60 40 20 0 0 10 20 30 40 50 60 70 80 ICC ICCS 100 80 60 40 20 0 2.7 3 3.3 3.6 3.9 ICC ICCS Internal frequency [MHz] VOL - External VCC Internal frequency = 68 MHz, Ta = + 25 C 0.8 0.6 0.4 0.2 0 2.7 4 3 External VCC [V] VOH - External VCC Internal frequency = 68 MHz, Ta = + 25 C VOH [V] 3 3.3 3.6 3.9 VOL [V] 2 1 0 2.7 3 3.3 3.6 3.9 External VCC [V] IIL - External VCC Internal frequency = 68 MHz, Ta = + 25 C 0 100 External VCC [V] IIL [A] 200 300 400 2.7 3 3.3 3.6 3.9 External VCC [V] 131 MB91301 Series ORDERING IMFORMATION Part No. MB91302APFF-G-001-BNDE1 MB91302APFF-G-010-BNDE1 MB91302APFF-G-020-BNDE1 MB91302APFF-G-XXX-BNDE1 MB91V301A-RDK01* 179-pin Ceramic PGA (PGA-179C-A03) 179-pin Ceramic PGA (PGA-179C-A03) 144-pin Plastic LQFP (FPT-144P-M12) Package Without ROM Optional real time OS internal model Built-in IPL (Internal Program Loader) version User ROM version Development pack for MB91302A real time OS internal model (MB91V301A and CD-ROM for development) Evaluation chip Remarks MB91V301A * : In case of buying this product, it is necessary to make a contract with "MB91V301A-RDK01 Fujitsu software product use contract". 132 MB91301 Series PACKAGE DIMENSIONS 144-pin Plastic LQFP (FPT-144P-M12) Note 1) * : These dimensions include resin protrusion. Resin protrusion is +0.25 (.010) Max (each side) . Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 18.000.20(.709.008)SQ +0.40 +.016 *16.00 -0.10 .630 -.004 SQ 108 73 109 72 0.08(.003) Details of "A" part 1.50 -0.10 .059 -.004 +0.20 +.008 (Mounting height) INDEX 0~8 144 37 "A" 0.600.15 (.024.006) 0.100.05 (.004.002) (Stand off) 0.25(.010) LEAD No. 1 36 +0.05 +.002 0.40(.016) 0.180.035 .007.001 0.07(.003) M 0.145 -0.03 .006 -.001 C 2003 FUJITSU LIMITED F144024S-c-3-3 Dimensions in mm (inches) Note : The values in parentheses are reference values. (Continued) 133 MB91301 Series (Continued) 179-pin Ceramic PGA (PGA-179C-A03) 2.540.25 (.100.010) 1.27(.050)TYP DIA 35.56(1.400) REF INDEX INDEX AREA 0.46 -0.05 DIA .018 -.002 38.100.51 SQ (1.500.020) 6.10(.240) MAX +.007 +0.18 1.270.25 (.050.010) 3.40 -0.36 .134 -.014 +0.41 +.016 C 1994 FUJITSU LIMITED R179004SC-3-2 Dimensions in mm (inches) Note : The values in parentheses are reference values. 134 MB91301 Series The information for microcontroller supports is shown in the following homepage. http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party's intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. F0512 (c) 2005 FUJITSU LIMITED Printed in Japan